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Features
* 80C52 Compatible
- 8051 Pin and Instruction Compatible - Four 8-bit I/O Ports - Three 16-bit Timer/Counters - 256 Bytes Scratch Pad RAM - 9 Interrupt Sources with 4 Priority Levels - Dual Data Pointer Variable Length MOVX for Slow RAM/Peripherals ISP (In-system Programming) Using Standard VCC Power Supply Boot ROM Contains Low Level Flash Programming Routines and a Default Serial Loader High-speed Architecture - 48 MHz in Standard Mode and Internal Code Execution (40 MHz for external code) - 24 MHz in X2 Mode and internal code execution (20 MHz for external code) - 16K/32K Bytes On-chip Flash Program/Data Memory - Byte and Page (128 Bytes) Erase and Write - 100K Write Cycles On-chip 1024 Bytes Expanded RAM (XRAM) - Software Selectable Size (0, 256, 512, 768, 1024 Bytes) - 256 Bytes Selected at Reset for TS87C51RB2/RC2 Compatibility Keyboard Interrupt Interface on Port P1 SPI Interface (Master/Slave Mode) 8-bit Clock Prescaler Improved X2 Mode with Independent Selection for CPU and Each Peripheral Programmable Counter Array 5 Channels - High-speed Output - Compare/Capture - Pulse Width Modulator - Watchdog Timer Capabilities Asynchronous Port Reset Full Duplex Enhanced UART Dedicated Baud Rate Generator for UART Low EMI (Inhibit ALE) Hardware Watchdog Timer (One-time Enabled with Reset-out) Power Control Modes - Idle Mode - Power-down Mode - Power-off Flag Power Supply: - 2.7 to 3.6 (3V Version) - 2.7 to 5.5V (5V Version) Temperature Ranges: Commercial (0 to +70C) and Industrial (-40C to +85C) Packages: PDIL40, PLCC44, VQFP44
* * * *
8-bit Microcontroller with 16K/ 32K Bytes Flash AT89C51RB2 AT89C51RC2
* * * * * *
* * * * * *
* * *
Description
The AT89C51RB2/RC2 is a high-performance Flash version of the 80C51 8-bit microcontrollers. It contains a 16K or 32K Bytes Flash memory block for program and data. The Flash memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software. The programming voltage is internally generated from the standard VCC pin. The AT89C51RB2/RC2 retains all features of the 80C52 with 256 Bytes of internal RAM, a 9-source 4-level interrupt controller and three timer/counters.
Rev. 4180B-8051-04/03
In addition, the AT89C51RB2/RC2 has a Programmable Counter Array, an XRAM of 1024 Bytes, a Hardware Watchdog Timer, a Keyboard Interface, an SPI Interface, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a speed improvement mechanism (X2 mode). The Pinout is the standard 40/44 pins of the C52. The fully static design reduces system power consumption of the AT89C51RB2/RC2 by allowing it to bring the clock frequency down to any value, even DC, without loss of data. The AT89C51RB2/RC2 has 2 software-selectable modes of reduced activity and 8-bit clock prescaler for further reduction in power consumption. In Idle mode, the CPU is frozen while the peripherals and the interrupt system are still operating. In power-down mode, the RAM is saved and all other functions are inoperative. The added features of the AT89C51RB2/RC2 make it more powerful for applications that need pulse width modulation, high speed I/O and counting capabilities such as alarms, motor control, corded phones, and smart card readers. Table 1. Memory Size
Part Number AT89C51RB2 AT89C51RC2 Flash (Bytes) 16K 32K XRAM (Bytes) 1024 1024 TOTAL RAM (Bytes) 1280 1280 I/O 32 32
Block Diagram
Figure 1. Block Diagram
T2EX PCA RxD TxD Vss VCC ECI T2 (1) SPI (1) (1) (1) (1) MISO P1 P2 P3 MOSI SCK P0
(2) (2) XTAL1 XTAL2
(1) Boot ROM 2Kx8
(1) (1)
EUART + BRG
RAM 256x8
Flash 32Kx8 or 16Kx8
XRAM
1Kx8
PCA
Timer2
ALE/ PROG PSEN CPU EA RD WR (2) (2)
C51 CORE
IB-bus
Timer 0 Timer 1
INT Ctrl
Parallel I/O Ports & Ext. Bus Port 0 Port 1 Port 2 Port 3
Watch Key Dog Board
(2) (2) RESET T0 T1
(2) (2) INT0 INT1
Notes:
1. Alternate function of Port 1. 2. Alternate function of Port 3.
2
AT89C51RB2/RC2
4180B-8051-04/03
SS
AT89C51RB2/RC2
SFR Mapping
The Special Function Registers (SFRs) of the AT89C51RB2/RC2 fall into the following categories: * * * * * * * * * * * * * * C51 core registers: ACC, B, DPH, DPL, PSW, SP I/O port registers: P0, P1, P2, P3 Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H Serial I/O port registers: SADDR, SADEN, SBUF, SCON PCA (Programmable Counter Array) registers: CCON, CCAPMx, CL, CH, CCAPxH, CCAPxL (x: 0 to 4) Power and clock control registers: PCON Hardware Watchdog Timer registers: WDTRST, WDTPRG Interrupt system registers: IEN0, IPL0, IPH0, IEN1, IPL1, IPH1 Keyboard Interface registers: KBE, KBF, KBLS SPI registers: SPCON, SPSTR, SPDAT BRG (Baud Rate Generator) registers: BRL, BDRCON Flash register: FCON Clock Prescaler register: CKRL Others: AUXR, AUXR1, CKCON0, CKCON1
3
4180B-8051-04/03
Table 2. C51 Core SFRs
Mnemonic ACC B PSW SP DPL DPH Add E0h F0h D0h 81h 82h 83h Name Accumulator B Register Program Status Word Stack Pointer Data Pointer Low Byte Data Pointer High Byte CY AC F0 RS1 RS0 OV F1 P 7 6 5 4 3 2 1 0
Table 3. System Management SFRs
Mnemonic PCON AUXR AUXR1 CKRL Add 87h 8Eh A2h 85h Name Power Control Auxiliary Register 0 Auxiliary Register 1 Clock Reload Register 7 SMOD1 DPU CKRL7 6 SMOD0 CKRL6 5 M0 ENBOOT CKRL5 4 XRS2 CKRL4 3 GF1 XRS1 GF3 CKRL3 2 GF0 XRS0 0 CKRL2 1 PD EXTRAM CKRL1 0 IDL AO DPS CKRL0
Table 4. Interrupt SFRs
Mnemonic IEN0 IEN1 IPH0 IPL0 IPH1 IPL1 Add A8h B1h B7h B8h B3h B2h Name Interrupt Enable Control 0 Interrupt Enable Control 1 Interrupt Priority Control High 0 Interrupt Priority Control Low 0 Interrupt Priority Control High 1 Interrupt Priority Control Low 1 7 EA 6 EC PPCH PPCL 5 ET2 PT2H PT2L 4 ES PHS PLS 3 ET1 PT1H PT1L 2 EX1 ESPI PX1H PX1L SPIH SPIL 1 ET0 EI2C PT0H PT0L IE2CH IE2CL 0 EX0 KBD PX0H PX0L KBDH KBDL
Table 5. Port SFRs
Mnemonic P0 P1 P2 P3 Add 80h 90h A0h B0h Name 8-bit Port 0 8-bit Port 1 8-bit Port 2 8-bit Port 3 7 6 5 4 3 2 1 0
4
AT89C51RB2/RC2
4180B-8051-04/03
AT89C51RB2/RC2
Table 6. Timer SFRs
Mnemonic TCON TMOD TL0 TH0 TL1 TH1 WDTRST WDTPRG T2CON T2MOD RCAP2H Add 88h 89h 8Ah 8Ch 8Bh 8Dh A6h A7h
C8h C9h CBh
Name Timer/Counter 0 and 1 Control Timer/Counter 0 and 1 Modes Timer/Counter 0 Low Byte Timer/Counter 0 High Byte Timer/Counter 1 Low Byte Timer/Counter 1 High Byte Watchdog Timer Reset Watchdog Timer Program
Timer/Counter 2 control Timer/Counter 2 Mode Timer/Counter 2 Reload/Capture High Byte Timer/Counter 2 Reload/Capture Low Byte
7 TF1 GATE1
6 TR1 C/T1#
5 TF0 M11
4 TR0 M01
3 IE1 GATE0
2 IT1 C/T0#
1 IE0 M10
0 IT0 M00
TF2 -
EXF2 -
RCLK -
TCLK -
EXEN2 -
WTO2
TR2 -
WTO1
C/T2# T2OE
WTO0
CP/RL2# DCEN
RCAP2L TH2 TL2
CAh CDh CCh
Timer/Counter 2 High Byte Timer/Counter 2 Low Byte
Table 7. PCA SFRs
Mnemonic
Add Name D8h D9h E9h F9h PCA Timer/Counter Control PCA Timer/Counter Mode PCA Timer/Counter Low Byte PCA Timer/Counter High Byte
7 CF CIDL
6 CR WDTE
5 -
4 CCF4 -
3 CCF3 -
2 CCF2 CPS1
1 CCF1 CPS0
0 CCF0 ECF
CCON CMOD CL CH
CCAPM0 DAh PCA Timer/Counter Mode 0 CCAPM1 DBh PCA Timer/Counter Mode 1 CCAPM2 DCh PCA Timer/Counter Mode 2 CCAPM3 DDh PCA Timer/Counter Mode 3 CCAPM4 DEh PCA Timer/Counter Mode 4 CCAP0H FAh CCAP1H FBh
ECOM0 ECOM1 ECOM2 ECOM3 ECOM4
CAPP0 CAPP1 CAPP2 CAPP3 CAPP4
CAPN0 CAPN1 CAPN2 CAPN3 CAPN4
MAT0 MAT1 MAT2 MAT3 MAT4
TOG0 TOG1 TOG2 TOG3 TOG4
PWM0 PWM1 PWM2 PWM3 PWM4
ECCF0 ECCF1 ECCF2 ECCF3 ECCF4
PCA Compare Capture Module 0 H CCAP0H7 CCAP0H6 CCAP0H5 CCAP0H4 CCAP0H3 CCAP0H2 CCAP0H1 CCAP0H0 PCA Compare Capture Module 1 H CCAP1H7 CCAP1H6 CCAP1H5 CCAP1H4 CCAP1H3 CCAP1H2 CCAP1H1 CCAP1H0
CCAP2H FCh PCA Compare Capture Module 2 H CCAP2H7 CCAP2H6 CCAP2H5 CCAP2H4 CCAP2H3 CCAP2H2 CCAP2H1 CCAP2H0 CCAP3H FDh PCA Compare Capture Module 3 H CCAP3H7 CCAP3H6 CCAP3H5 CCAP3H4 CCAP3H3 CCAP3H2 CCAP3H1 CCAP3H0 CCAP4H FEh CCAP0L CCAP1L CCAP2L CCAP3L CCAP4L PCA Compare Capture Module 4 H CCAP4H7 CCAP4H6 CCAP4H5 CCAP4H4 CCAP4H3 CCAP4H2 CCAP4H1 CCAP4H0
EAh PCA Compare Capture Module 0 L CCAP0L7 EBh PCA Compare Capture Module 1 L CCAP1L7 ECh PCA Compare Capture Module 2 L CCAP2L7 EDh PCA Compare Capture Module 3 L CCAP3L7 EEh PCA Compare Capture Module 4 L CCAP4L7
CCAP0L6 CCAP1L6 CCAP2L6 CCAP3L6 CCAP4L6
CCAP0L5 CCAP0L4 CCAP1L5 CCAP1L4 CCAP2L5 CCAP2L4 CCAP3L5 CCAP3L4 CCAP4L5 CCAP4L4
CCAP0L3 CCAP0L2 CCAP1L3 CCAP1L2 CCAP2L3 CCAP2L2 CCAP3L3 CCAP3L2 CCAP4L3 CCAP4L2
CCAP0L1 CCAP1L1 CCAP2L1 CCAP3L1 CCAP4L1
CCAP0L0 CCAP1L0 CCAP2L0 CCAP3L0 CCAP4L0
5
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Table 8. Serial I/O Port SFRs
Mnemonic SCON SBUF SADEN SADDR BDRCON BRL Add 98h 99h B9h A9h 9Bh 9Ah Name Serial Control Serial Data Buffer Slave Address Mask Slave Address Baud Rate Control Baud Rate Reload BRR TBCK RBCK SPD SRC 7 FE/SM0 6 SM1 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI
Table 9. SPI Controller SFRs
Mnemonic SPCON SPSTA SPDAT Add C3h C4h C5h Name SPI Control SPI Status SPI Data 7 SPR2 SPIF SPD7 6 SPEN WCOL SPD6 5 SSDIS SSERR SPD5 4 MSTR MODF SPD4 3 CPOL SPD3 2 CPHA SPD2 1 SPR1 SPD1 0 SPR0 SPD0
Table 10. Keyboard Interface SFRs
Mnemonic KBLS KBE KBF Add 9Ch 9Dh 9Eh Name Keyboard Level Selector Keyboard Input Enable Keyboard Flag Register 7 KBLS7 KBE7 KBF7 6 KBLS6 KBE6 KBF6 5 KBLS5 KBE5 KBF5 4 KBLS4 KBE4 KBF4 3 KBLS3 KBE3 KBF3 2 KBLS2 KBE2 KBF2 1 KBLS1 KBE1 KBF1 0 KBLS0 KBE0 KBF0
6
AT89C51RB2/RC2
4180B-8051-04/03
AT89C51RB2/RC2
Table 11 shows all SFRs with their address and their reset value. Table 11. SFR Mapping
Bit addressable 0/8 F8h B 0000 0000 CL 0000 0000 ACC 0000 0000 CCON 00X0 0000 PSW 0000 0000 T2CON 0000 0000 CMOD 00XX X000 FCON (1) XXXX 0000 T2MOD XXXX XX00 RCAP2L 0000 0000 RCAP2H 0000 0000 SPCON 0001 0100 IPL0 X000 000 P3 1111 1111 IEN0 0000 0000 P2 1111 1111 SCON 0000 0000 P1 1111 1111 TCON 0000 0000 P0 1111 1111 0/8 1. TMOD 0000 0000 SP 0000 0111 1/9 TL0 0000 0000 DPL 0000 0000 2/A TL1 0000 0000 DPH 0000 0000 3/B 4/C 5/D 6/E TH0 0000 0000 TH1 0000 0000 AUXR XX0X 0000 SBUF XXXX XXXX SADEN 0000 0000 IEN1 XXXXX 000 SADDR 0000 0000 AUXR1 XXXXX0X0 BRL 0000 0000 BDRCON XXX0 0000 KBLS 0000 0000 KBE 0000 0000 WDTRST XXXX XXXX KBF 0000 0000 CKRL 1111 1111 CKCON0 0000 0000 PCON 00X1 0000 7/F IPL1 XXXXX000 IPH1 XXXX X000 IPH0 X000 0000 CKCON1 XXXX XXX0 WDTPRG XXXX X000 TL2 0000 0000 SPSTA 0000 0000 TH2 0000 0000 SPDAT XXXX XXXX CCAPM0 X000 0000 CCAPM1 X000 0000 CCAPM2 X000 0000 CCAPM3 X000 0000 CCAPM4 X000 0000 CCAP0L XXXX XXXX CCAP1L XXXX XXXX CCAPL2L XXXX XXXX CCAPL3L XXXX XXXX CCAPL4L XXXX XXXX 1/9 CH 0000 0000 2/A CCAP0H XXXX 3/B CCAP1H XXXX Non Bit addressable 4/C CCAPL2H XXXX 5/D CCAPL3H XXXX 6/E CCAPL4H XXXX 7/F FFh
F0h
F7h
E8h
EFh
E0h
E7h
D8h D0h C8h C0h
DFh D7h CFh C7h
B8h
BFh
B0h
B7h
A8h
AFh
A0h
A7h
98h
9Fh
90h
97h
88h
8Fh
80h
87h
FCON access is reserved for the Flash API and ISP software.
Reserved
7
4180B-8051-04/03
Pin Configurations
Figure 2. Pin Configurations
P0.2/AD2 P0.3/AD3 39 38 37 36 35 34 33 32 31 30 29 P0.0/AD0 P0.1/AD1 P1.2/ECI P1.0/T2 P1.1/T2EX/SS P1.2/ECI P1.3CEX0 P1.4/CEX1 P1.5/CEX2/MISO P1.6/CEX3/SCK P1.7CEX4/MOSI RST P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA ALE/PROG PSEN P2.7/AD15 P2.6/AD14 P2.5/AD13 P2.4/AD12 P2.3/AD11 P2.2/AD10 P2.1/AD9 P2.0/AD8 P1.5/CEX2/MISO P1.6/CEX3/SCK P1.7/CEx4/MOSI RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 7 8 9 10 11 12 13 14 15 16 17 P1.1/T2EX/SS P1.4/CEX1 P1.3/CEX0
P1.0/T2
NIC*
6 5 4 3 2 1 44 43 42 41 40 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA NIC* ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13
PDIL40
PLCC44
18 19 20 21 22 23 24 25 26 27 28
P3.6/WR P2.2/A10 P2.3/A11 P2.4/A12 4180B-8051-04/03 P3.7/RD NIC* P2.0/A8 P2.1/A9 XTAL2 XTAL1 VSS
P1.1/T2EX/SS
P1.4/CEX1
P1.3/CEX0
P0.0/AD0
P0.1/AD1
P0.2/AD2
44 43 42 41 40 39 38 37 36 35 34 P1.5/CEX2/MISO P1.6/CEX3/SCK P1.7/CEX4/MOSI RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA NIC* ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13
VQFP44 1.4
12 13 14 15 16 17 18 19 20 21 22
P2.3/A11 P2.4/A12 XTAL2 XTAL1 NIC* P2.0/A8 P3.6/WR P3.7/RD P2.1/A9 P2.2/A10 VSS
*NIC: No Internal Connection
8
AT89C51RB2/RC2
P0.3/AD3
P1.2/ECI
P1.0/T2
NIC*
VCC
VCC
AT89C51RB2/RC2
Table 12. Pin Description for 40 - 44 Pin Packages
Pin Number Mnemonic VSS VCC P0.0 - P0.7 DIL 20 40 39 - 32 LCC 22 44 43 - 36 VQFP44 1.4 16 38 37 - 30 Type I I I/O Name and Function Ground: 0V reference Power Supply: This is the power supply voltage for normal, idle and power-down operation Port 0: Port 0 is an open-drain, bi-directional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. Port 0 must be polarized to VCC or VSS in order to prevent any parasitic current consumption. Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. In this application, it uses strong internal pull-up when emitting 1s. Port 0 also inputs the code Bytes during Flash programming. External pull-ups are required during program verification during which P0 outputs the code Bytes. Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pull-ups. Port 1 also receives the low-order address Byte during memory programming and verification. Alternate functions for AT89C51RB2/RC2 Port 1 include: 1 2 40 I/O I/O 2 3 41 I/O I I 3 4 42 I/O I 4 5 43 I/O I/O 5 6 44 I/O I/O 6 7 1 I/O I/O I/O P1.0: Input/Output T2 (P1.0): Timer/Counter 2 external count input/Clockout P1.1: Input/Output T2EX: Timer/Counter 2 Reload/Capture/Direction Control SS: SPI Slave Select P1.2: Input/Output ECI: External Clock for the PCA P1.3: Input/Output CEX0: Capture/Compare External I/O for PCA Module 0 P1.4: Input/Output CEX1: Capture/Compare External I/O for PCA Module 1 P1.5: Input/Output CEX2: Capture/Compare External I/O for PCA Module 2 MISO: SPI Master Input Slave Output line When SPI is in master mode, MISO receives data from the slave peripheral. When SPI is in slave mode, MISO outputs data to the master controller. 7 8 2 I/O I/O I/O P1.6: Input/Output CEX3: Capture/Compare External I/O for PCA Module 3 SCK: SPI Serial Clock SCK outputs clock to the slave peripheral 8 9 3 I/O P1.7: Input/Output:
P1.0 - P1.7
1-8
2-9
40 - 44 1-3
I/O
9
4180B-8051-04/03
Table 12. Pin Description for 40 - 44 Pin Packages (Continued)
Pin Number Mnemonic DIL LCC VQFP44 1.4 Type I/O P1.0 - P1.7 I/O Name and Function CEX4: Capture/Compare External I/O for PCA Module 4 MOSI: SPI Master Output Slave Input line When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI is in slave mode, MOSI receives data from the master controller. XTAL1 XTAL2 P2.0 - P2.7 19 18 21 - 28 21 20 24 - 31 15 14 18 - 25 I O I/O Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pull-ups. Port 2 emits the high - order address Byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR. Some Port 2 pins receive the high order address bits during EPROM programming and verification: P2.0 to P2.5 for 16 KB devices P2.0 to P2.6 for 32KB devices P3.0 - P3.7 10 - 17 11, 13 - 19 5, 7 - 13 I/O Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pull-ups. Port 3 also serves the special features of the 80C51 family, as listed below. RXD (P3.0): Serial input port TXD (P3.1): Serial output port INT0 (P3.2): External interrupt 0 INT1 (P3.3): External interrupt 1 T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. This pin is an output when the hardware watchdog forces a system reset. Address Latch Enable/Program Pulse: Output pulse for latching the low Byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during Flash programming. ALE can be disabled by setting SFR's AUXR. 0 bit. With this bit set, ALE will be inactive during internal fetches.
10 11 12 13 14 15 16 17
11 13 14 15 16 17 18 19
5 7 8 9 10 11 12 13
I O I I I I O O
RST
9
10
4
I/O
ALE/PROG
30
33
27
O (I)
10
AT89C51RB2/RC2
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AT89C51RB2/RC2
Table 12. Pin Description for 40 - 44 Pin Packages (Continued)
Pin Number Mnemonic PSEN DIL 29 LCC 32 VQFP44 1.4 26 Type O Name and Function Program Strobe Enable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. External Access Enable: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to FFFFH (RD). If security level 1 is programmed, EA will be internally latched on Reset.
EA
31
35
29
I
11
4180B-8051-04/03
Oscillator
To optimize the power consumption and execution time needed for a specific task, an internal, prescaler feature has been implemented between the oscillator and the CPU and peripherals. Table 13. CKRL Register CKRL - Clock Reload Register (97h)
7 CKRL7 Bit Number 7:0 6 CKRL6 5 CKRL5 4 CKRL4 Description Clock Reload Register Prescaler value 3 CKRL3 2 CKRL2 1 CKRL1 0 CKRL0
Registers
Mnemonic CKRL
Reset Value = 1111 1111b Not bit addressable Table 14. PCON Register PCON - Power Control Register (87h)
7 SMOD1 Bit Number 7 6 SMOD0 5 4 POF Description Serial Port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3. Serial Port Mode bit 0 Cleared to select SM0 bit in SCON register. Set to select FE bit in SCON register. Reserved The value read from this bit is indeterminate. Do not set this bit. Power-off Flag Cleared to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. General-purpose Flag Cleared by software for general-purpose usage. Set by software for general-purpose usage. General-purpose Flag Cleared by software for general-purpose usage. Set by software for general-purpose usage. Power-down Mode bit Cleared by hardware when reset occurs. Set to enter power-down mode. Idle Mode bit Cleared by hardware when interrupt or reset occurs. Set to enter idle mode. 3 GF1 2 GF0 1 PD 0 IDL
Bit Mnemonic SMOD1
6
SMOD0
5
-
4
POF
3
GF1
2
GF0
1
PD
0
IDL
Reset Value = 00X1 0000b Not bit addressable
12
AT89C51RB2/RC2
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AT89C51RB2/RC2
Functional Block Diagram
Figure 3. Functional Oscillator Block Diagram
Reset CKRL Xtal1 Osc Xtal2 :2 FOSC 1 0 8-bit Prescaler-Divider 1 X2 CLK PERIPH CLK CPU Peripheral Clock CPU clock Reload
CKCON0
0
Idle
CKRL = 0xFF?
Prescaler Divider
*
A hardware RESET puts the prescaler divider in the following state: * CKRL = FFh: FCLK CPU = FCLK PERIPH = FOSC/2 (Standard C51 feature)
*
Any value between FFh down to 00h can be written by software into CKRL register in order to divide frequency of the selected oscillator: * CKRL = 00h: minimum frequency FCLK CPU = FCLK PERIPH = FOSC/1020 (Standard Mode) FCLK CPU = FCLK PERIPH = FOSC/510 (X2 Mode) CKRL = FFh: maximum frequency FCLK CPU = FCLK PERIPH = FOSC/2 (Standard Mode) FCLK CPU = FCLK PERIPH = FOSC (X2 Mode)
*
FCLK CPU and FCLK PERIPH In X2 Mode, for CKRL<>0xFF: F OSC F CPU = F CLKPERIPH = ---------------------------------------------In X1 Mode, for CKRL<>0xFF then: F OSC F CPU = F CLKPERIPH = ----------------------------------------------
2 x ( 255 - CKRL )
4 x ( 255 - CKRL )
13
4180B-8051-04/03
Enhanced Features
In comparison to the original 80C52, the AT89C51RB2/RC2 implements some new features, which are: * * * * * * * * * * * X2 option Dual Data Pointer Extended RAM Programmable Counter Array (PCA) Hardware Watchdog SPI interface 4-level interrupt priority system power-off flag ONCE mode ALE disabling Some enhanced features are also located in the UART and the timer 2
X2 Feature
The AT89C51RB2/RC2 core needs only 6 clock periods per machine cycle. This feature called `X2' provides the following advantages: * * * * Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power. Save power consumption while keeping same CPU power (oscillator power saving). Save power consumption by dividing dynamically the operating frequency by 2 in operating and idle modes. Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by software. Description The clock for the whole circuit and peripherals is first divided by 2 before being used by the CPU core and the peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 4 shows the clock generation block diagram. X2 bit is validated on the rising edge of the XTAL1/2 to avoid glitches when switching from X2 to X1 mode. Figure 5 shows the switching mode waveforms. Figure 4. Clock Generation Diagram
CKRL XTAL1 FXTAL 2 XTAL1:2 0 1 FOSC 8 bit Prescaler FCLK CPU FCLK PERIPH
X2 CKCON0
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Figure 5. Mode Switching Waveforms
XTAL1
XTAL1:2
X2 Bit
CPU Clock x1 Mode
FOSC X2 Mode X1 Mode
The X2 bit in the CKCON0 register (see Table 15) allows a switch from 12 clock periods per instruction to 6 clock periods and vice versa. At reset, the speed is set according to X2 bit of Hardware Security Byte (HSB). By default, Standard mode is active. Setting the X2 bit activates the X2 feature (X2 mode). The T0X2, T1X2, T2X2, UARTX2, PCAX2, and WDX2 bits in the CKCON0 register (Table 15) and SPIX2 bit in the CKCON1 register (see Table 16) allow a switch from standard peripheral speed (12 clock periods per peripheral clock cycle) to fast peripheral speed (6 clock periods per peripheral clock cycle). These bits are active only in X2 mode.
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Table 15. CKCON0 Register CKCON0 - Clock Control Register (8Fh)
7 Bit Number 7 6 WDX2 Bit Mnemonic Description Reserved Watchdog Clock 6 WDX2 (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Programmable Counter Array Clock 5 PCAX2 (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Enhanced UART Clock (Mode 0 and 2) 4 SIX2 (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Timer 2 Clock 3 T2X2 (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Timer 1 Clock 2 T1X2 (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Timer0 Clock 1 T0X2 (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. CPU Clock 0 X2 Cleared to select 12 clock periods per machine cycle (STD, X1 mode) for CPU and all the peripherals. Set to select 6 clock periods per machine cycle (X2 mode) and to enable the individual peripherals'X2' bits. Programmed by hardware after Power-up regarding Hardware Security Byte (HSB), Default setting, X2 is cleared. 5 PCAX2 4 SIX2 3 T2X2 2 T1X2 1 T0X2 0 X2
Reset Value = 0000 000'HSB. X2'b (see Table 65 "Hardware Security Byte") Not bit addressable
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Table 16. CKCON1 Register CKCON1 - Clock Control Register (AFh)
7 Bit Number 7 6 5 4 3 2 1 6 Bit Mnemonic Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 5 4 3 2 1 0 SPIX2
0
SPIX2
Reset Value = XXXX XXX0b Not bit addressable
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Dual Data Pointer Register (DPTR)
The additional data pointer can be used to speed up code execution and reduce code size. The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1.0 (see Table 17) that allows the program code to switch between them (see Figure 6).
Figure 6. Use of Dual Pointer
External Data Memory
7
0 DPS
DPTR1 DPTR0
AUXR1(A2H)
DPH(83H) DPL(82H)
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Table 17. AUXR1 register AUXR1- Auxiliary Register 1(0A2h)
7 Bit Number 7 6 Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Enable Boot Flash Cleared to disable boot ROM. Set to map the boot ROM between F800h - 0FFFFh. 4 3 2 1 GF3 0 Reserved The value read from this bit is indeterminate. Do not set this bit. This bit is a general-purpose user flag.(1) Always Cleared Reserved The value read from this bit is indeterminate. Do not set this bit. Data Pointer Selection Cleared to select DPTR0. Set to select DPTR1. 5 ENBOOT 4 3 GF3 2 0 1 0 DPS
6
-
5
ENBOOT
0
DPS
Reset Value = XXXX XX0X0b Not bit addressable
Note: 1. Bit 2 stuck at 0; this allows using INC AUXR1 to toggle DPS without changing GF3.
ASSEMBLY LANGUAGE ; Block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 EQU 0A2H ; 0000 909000MOV DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ; switch data pointers 0005 90A000 MOV DPTR,#DEST ; address of DEST 0008 LOOP: 0008 05A2 INC AUXR1 ; switch data pointers 000A E0 MOVX A,@DPTR ; get a Byte from SOURCE 000B A3 INC DPTR ; increment SOURCE address 000C 05A2 INC AUXR1 ; switch data pointers 000E F0 MOVX @DPTR,A ; write the Byte to DEST 000F A3 INC DPTR ; increment DEST address 0010 70F6JNZ LOOP ; check for 0 terminator 0012 05A2 INC AUXR1 ; (optional) restore DPS
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INC is a short (2 Bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state.
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Expanded RAM (XRAM)
The AT89C51RB2/RC2 provides additional bytes of random access memory (RAM) space for increased data parameter handling and high-level language usage. AT89C51RB2/RC2 devices have expanded RAM in external data space; maximum size and location are described in Table 18. Table 18. Expanded RAM
Address Part Number AT89C51RB2/RC2 XRAM Size 1024 Start 00h End 3FFh
The AT89C51RB2/RC2 has internal data memory that is mapped into four separate segments. The four segments are: 1. The Lower 128 Bytes of RAM (addresses 00h to 7Fh) are directly and indirectly addressable. 2. The Upper 128 Bytes of RAM (addresses 80h to FFh) are indirectly addressable only. 3. The Special Function Registers, SFRs, (addresses 80h to FFh) are directly addressable only. 4. The expanded RAM Bytes are indirectly accessed by MOVX instructions, and with the EXTRAM bit cleared in the AUXR register (see Table 18). The lower 128 Bytes can be accessed by either direct or indirect addressing. The Upper 128 Bytes can be accessed by indirect addressing only. The Upper 128 Bytes occupy the same address space as the SFR. That means they have the same address, but are physically separate from SFR space. Figure 7. Internal and External Data Memory Address
0FFh or 3FFh 0FFh Upper 128 Bytes Internal RAM Indirect Accesses XRAM 80h 7Fh Lower 128 Bytes Internal RAM Direct or Indirect Accesses 00 00 80h 0FFh 0FFFFh
Special Function Register Direct Accesses
External Data Memory
00FFh up to 03FFh 0000
When an instruction accesses an internal location above address 7Fh, the CPU knows whether the access is to the upper 128 Bytes of data RAM or to SFR space by the addressing mode used in the instruction. * Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data, accesses the SFR at location 0A0h (which is P2).
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*
Instructions that use indirect addressing access the Upper 128 Bytes of data RAM. For example: MOV @R0, # data where R0 contains 0A0h, accesses the data Byte at address 0A0h, rather than P2 (whose address is 0A0h). The XRAM Bytes can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions. This part of memory that is physically located on-chip, logically occupies the first Bytes of external data memory. The bits XRS0 and XRS1 are used to hide a part of the available XRAM as explained in Table 18. This can be useful if external peripherals are mapped at addresses already used by the internal XRAM. With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. An access to XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For example, with EXTRAM = 0, MOVX @R0, # data where R0 contains 0A0H, accesses the XRAM at address 0A0H rather than external memory. An access to external data memory locations higher than the accessible size of the XRAM will be performed with the MOVX DPTR instructions in the same way as in the standard 80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and read timing signals. Accesses to XRAM above 0FFH can only be done by the use of DPTR. With EXTRAM = 1, MOVX @RI and MOVX @DPTR will be similar to the standard 80C51. MOVX @ Ri will provide an eight-bit address multiplexed with data on Port0 and any output port pins can be used to output higher order address bits. This is to provide the external paging capability. MOVX @DPTR will generate a sixteen-bit address. Port2 outputs the high-order eight address bits (the contents of DPH) while Port0 multiplexes the low-order eight address bits (DPL) with data. MOVX @ RI and MOVX @DPTR will generate either read or write signals on P3.6 (WR) and P3.7 (RD).
*
*
*
The stack pointer (SP) may be located anywhere in the 256 Bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the XRAM. The M0 bit allows to stretch the XRAM timings; if M0 is set, the read and write pulses are extended from 6 to 30 clock periods. This is useful to access external slow peripherals.
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Registers
Table 19. AUXR Register AUXR - Auxiliary Register (8Eh)
7 DPU Bit Number 6 Bit Mnemonic Description Disable Weak Pull-up 7 DPU Cleared to activate the permanent weak pull up when latch data is logical 1 Set to disactive the weak pull-up (reduce power consumption) 6 Reserved The value read from this bit is indeterminate. Do not set this bit. Pulse Length 5 M0 Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock periods (default). Set to stretch MOVX control: the RD and the WR pulse length is 30 clock periods. 4 3 XRS1 Reserved The value read from this bit is indeterminate. Do not set this bit. XRAM Size XRS1 XRS0 XRAM size 0 0 256 Bytes (default) 2 XRS0 0 1 1 1 0 1 512 Bytes 768 Bytes 1024 Bytes 5 M0 4 3 XRS1 2 XRS0 1 EXTRAM 0 AO
EXTRAM Bit Cleared to access internal XRAM using movx @ Ri/ @ DPTR. 1 EXTRAM Set to access external memory. Programmed by hardware after Power-up regarding Hardware Security Byte (HSB), default setting, XRAM selected. ALE Output Bit Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode is used). (default) Set, ALE is active only during a MOVX or MOVC instruction is used.
0
AO
Reset Value = XX0X 00'HSB. XRAM'0b (see Table 65) Not bit addressable
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Timer 2
The Timer 2 in the AT89C51RB2/RC2 is the standard C52 Timer 2. It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 are cascaded. It is controlled by T2CON (Table 20) and T2MOD (Table 21) registers. Timer 2 operation is similar to Timer 0 and Timer 1C/T2 selects FOSC/12 (timer operation) or external pin T2 (counter operation) as the timer clock input. Setting TR2 allows TL2 to increment by the selected input. Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON). see the Atmel 8-bit Microcontroller Hardware description for the description of Capture and Baud Rate Generator Modes. Timer 2 includes the following enhancements: * * Auto-reload mode with up or down counter Programmable clock-output
Auto-reload Mode
The auto-reload mode configures Timer 2 as a 16-bit timer or event counter with automatic reload. If DCEN bit in T2MOD is cleared, Timer 2 behaves as in 80C52 (see the Atmel C51 Microcontroller Hardware description). If DCEN bit is set, Timer 2 acts as an Up/down timer/counter as shown in Figure 8. In this mode the T2EX pin controls the direction of count. When T2EX is high, Timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2. When T2EX is low, Timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh into the timer registers. The EXF2 bit toggles when Timer 2 overflows or underflows according to the direction of the count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit resolution.
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Figure 8. Auto-Reload Mode Up/Down Counter (DCEN = 1) FCLK PERIPH :6
T2 C/T2 T2CON TR2 T2CON 0 1
T2EX: (DOWN COUNTING RELOAD VALUE) if DCEN = 1, 1 = UP FFh FFh if DCEN = 1, 0 = DOWN (8-bit) (8-bit) if DCEN = 0, up counting
TOGGLE T2CON EXF2
TL2
(8-bit)
TH2
(8-bit)
TF2 T2CON
TIMER 2 INTERRUPT
RCAP2L (8-bit)
RCAP2H (8-bit)
(UP COUNTING RELOAD VALUE)
Programmable Clock-out In the clock-out mode, Timer 2 operates as a 50% duty-cycle, programmable clock generator (see Figure 9). The input clock increments TL2 at frequency FCLK PERIPH/2. The Mode
timer repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, Timer 2 overflows do not generate interrupts. The formula gives the clock-out frequency as a function of the system oscillator frequency and the value in the RCAP2H and RCAP2L registers: F CLKPERIPH Clock - O utFrequency = -------------------------------------------------------------------------------------------4 x ( 65536 - RCAP2H RCAP2L ) For a 16 MHz system clock, Timer 2 has a programmable frequency range of 61 Hz (FCLK PERIPH/216) to 4 MHz (FCLK PERIPH/4). The generated clock signal is brought out to T2 pin (P1.0). Timer 2 is programmed for the clock-out mode as follows: * * * * * Set T2OE bit in T2MOD register. Clear C/T2 bit in T2CON register. Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers. Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or a different one depending on the application. To start the timer, set TR2 run control bit in T2CON register.
It is possible to use Timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers.
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Figure 9. Clock-Out Mode C/T2 = 0
FCLK PERIPH :6
TR2
T2CON
TL2 (8-bit)
TH2 (8-bit)
OVERFLOW
RCAP2L RCAP2H (8-bit) (8-bit)
Toggle T2
Q
D T2OE T2MOD
T2EX EXEN2 T2CON
EXF2 T2CON
TIMER 2 INTERRUPT
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Registers
Table 20. T2CON Register T2CON - Timer 2 Control Register (C8h)
7 TF2 Bit Number 6 EXF2 Bit Mnemonic Description Timer 2 Overflow Flag Must be cleared by software. Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0. Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2 = 1. When set, causes the CPU to vector to Timer 2 interrupt routine when Timer 2 interrupt is enabled. Must be cleared by software. EXF2 doesn't cause an interrupt in Up/down counter mode (DCEN = 1). Receive Clock Bit Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3. Transmit Clock Bit Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3. Timer 2 External Enable Bit Cleared to ignore events on T2EX pin for Timer 2 operation. Set to cause a capture or reload when a negative transition on T2EX pin is detected, if Timer 2 is not used to clock the serial port. Timer 2 Run Control Bit Cleared to turn off Timer 2. Set to turn on Timer 2. Timer/Counter 2 Select Bit Cleared for timer operation (input from internal clock system: FCLK PERIPH). Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode. Timer 2 Capture/Reload Bit If RCLK = 1 or TCLK = 1, CP/RL2# is ignored and timer is forced to auto-reload on Timer 2 overflow. Cleared to auto-reload on Timer 2 overflows or negative transitions on T2EX pin if EXEN2 = 1. Set to capture on negative transitions on T2EX pin if EXEN2 = 1. 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 C/T2# 0 CP/RL2#
7
TF2
6
EXF2
5
RCLK
4
TCLK
3
EXEN2
2
TR2
1
C/T2#
0
CP/RL2#
Reset Value = 0000 0000b Bit addressable
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Table 21. T2MOD Register T2MOD - Timer 2 Mode Control Register (C9h)
7 Bit Number 7 6 Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Timer 2 Output Enable Bitt Cleared to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output. Down Counter Enable Bit Cleared to disable Timer 2 as up/down counter. Set to enable Timer 2 as up/down counter. 5 4 3 2 1 T2OE 0 DCEN
6
-
5
-
4
-
3
-
2
-
1
T2OE
0
DCEN
Reset Value = XXXX XX00b Not bit addressable
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Programmable Counter Array (PCA)
The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture Modules. Its clock input can be programmed to count any one of the following signals: * * * * * * * *
/6 Peripheral clock frequency (FCLK PERIPH) / 2
Peripheral clock frequency (FCLK PERIPH) Timer 0 overflow External input on ECI (P1.2) Rising and/or falling edge capture Software timer High-speed output Pulse width modulator
Each compare/capture Modules can be programmed in any one of the following modes:
Module 4 can also be programmed as a watchdog timer (see Section "PCA Watchdog Timer", page 40). When the compare/capture Modules are programmed in the capture mode, software timer, or high speed output mode, an interrupt can be generated when the Module executes its function. All five Modules plus the PCA timer overflow share one interrupt vector.
The PCA timer/counter and compare/capture modules share Port 1 for external I/O. These pins are listed below. If one or several bits in the port are not used for the PCA, they can still be used for standard I/O.
PCA Component 16-bit Counter 16-bit Module 0 16-bit Module 1 16-bit Module 2 16-bit Module 3 External I/O Pin P1.2/ECI P1.3/CEX0 P1.4/CEX1 P1.5/CEX2 P1.6/CEX3
The PCA timer is a common time base for all five Modules (see Figure 10). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD register (Table 22) and can be programmed to run at: * * * * 1/6 the peripheral clock frequency (FCLK PERIPH) 1/2 the peripheral clock frequency (FCLK PERIPH) The Timer 0 overflow The input on the ECI pin (P1.2)
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Figure 10. PCA Timer/Counter
To PCA Modules FCLK PERIPH/6 FCLK PERIPH/2 T0 OVF P1.2 overflow CH CL 16-bit Up/Down Counter It
CIDL Idle
WDTE
CPS1
CPS0
ECF
CMOD 0xD9
CF
CR
CCF4 CCF3
CCF2
CCF1
CCF0
CCON 0xD8
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Registers
Table 22. CMOD Register CMOD - PCA Counter Mode Register (D9h)
7 CIDL Bit Number 6 WDTE Bit Mnemonic Description Counter Idle Control 7 CIDL Cleared to program the PCA Counter to continue functioning during idle Mode. Set to program PCA to be gated off during idle. Watchdog Timer Enable 6 WDTE Cleared to disable Watchdog Timer function on PCA Module 4. Set to enable Watchdog Timer function on PCA Module 4. 5 Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. PCA Count Pulse Select CPS1 CPS0 0 0 1 CPS0 0 1 1 1 0 1 Selected PCA input Internal clock FCLK PERIPH/6 Internal clock FLK PERIPH/2 Timer 0 Overflow External clock at ECI/P1.2 pin (max rate = fCLK PERIPH/ 4) 5 4 3 2 CPS1 1 CPS0 0 ECF
4
-
3 2
CPS1
0
ECF
PCA Enable Counter Overflow Interrupt Cleared to disable CF bit in CCON to inhibit an interrupt. Set to enable CF bit in CCON to generate an interrupt.
Reset Value = 00XX X000b Not bit addressable The CMOD register includes three additional bits associated with the PCA. * * * The CIDL bit which allows the PCA to stop during idle mode. The WDTE bit which enables or disables the watchdog function on Module 4. The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be set when the PCA timer overflows.
The CCON register contains the run control bit for the PCA and the flags for the PCA timer (CF) and each Module (see Table 23). * * Bit CR (CCON. 6) must be set by software to run the PCA. The PCA is shut off by clearing this bit. Bit CF: The CF bit (CCON. 7) is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by software. Bits 0 through 4 are the flags for the Modules (bit 0 for Module 0, bit 1 for Module 1, etc. ) and are set by hardware when either a match or a capture occurs. These flags also can only be cleared by software.
*
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Table 23. CCON Register CCON - PCA Counter Control Register (D8h)
7 CF Bit Number 6 CR Bit Mnemonic Description PCA Counter Overflow Flag 7 CF Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can only be cleared by software. PCA Counter Run Control Bit 6 CR Must be cleared by software to turn the PCA counter off. Set by software to turn the PCA counter on. 5 Reserved The value read from this bit is indeterminate. Do not set this bit. PCA Module 4 Interrupt Flag 4 CCF4 Must be cleared by software. Set by hardware when a match or capture occurs. PCA Module 3 Interrupt Flag 3 CCF3 Must be cleared by software. Set by hardware when a match or capture occurs. PCA Module 2 Interrupt Flag 2 CCF2 Must be cleared by software. Set by hardware when a match or capture occurs. PCA Module 1 Interrupt Flag 1 CCF1 Must be cleared by software. Set by hardware when a match or capture occurs. PCA Module 0 Interrupt Flag 0 CCF0 Must be cleared by software. Set by hardware when a match or capture occurs. 5 4 CCF4 3 CCF3 2 CCF2 1 CCF1 0 CCF0
Reset Value = 000X 0000b Not bit addressable The watchdog timer function is implemented in Module 4 (see Figure 13). The PCA interrupt system is shown in Figure 11.
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Figure 11. PCA Interrupt System
CF PCA Timer/Counter CR CCF4 CCF3 CCF2 CCF1 CCF0 CCON 0xD8
Module 0
Module 1
To Interrupt Priority Decoder
Module 2
Module 3
Module 4 CMOD. 0 ECF ECCFn CCAPMn. 0 IE. 6 EC IE. 7 EA
PCA Modules: each one of the five compare/capture Modules has six possible functions. It can perform: * * * * * * 16-bit Capture, positive-edge triggered 16-bit Capture, negative-edge triggered 16-bit Capture, both positive and negative-edge triggered 16-bit Software Timer 16-bit High-speed Output 8-bit Pulse Width Modulator
In addition, Module 4 can be used as a Watchdog Timer. Each Module in the PCA has a special function register associated with it. These registers are: CCAPM0 for Module 0, CCAPM1 for Module 1, etc. (see Table 24). The registers contain the bits that control the mode that each Module will operate in. * The ECCF bit (CCAPMn. 0 where n = 0, 1, 2, 3, or 4 depending on the Module) enables the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated Module. PWM (CCAPMn. 1) enables the pulse width modulation mode. The TOG bit (CCAPMn. 2) when set causes the CEX output associated with the Module to toggle when there is a match between the PCA counter and the Module's capture/compare register. The match bit MAT (CCAPMn. 3) when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the Module's capture/compare register. The next two bits CAPN (CCAPMn. 4) and CAPP (CCAPMn. 5) determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition. The last bit in the register ECOM (CCAPMn. 6) when set enables the comparator function.
* *
*
*
*
Table 24 shows the CCAPMn settings for the various PCA functions. 33
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Table 24. CCAPMn Registers (n = 0-4) CCAPM0 - PCA Module 0 Compare/Capture Control Register (0DAh) CCAPM1 - PCA Module 1 Compare/Capture Control Register (0DBh) CCAPM2 - PCA Module 2 Compare/Capture Control Register (0DCh) CCAPM3 - PCA Module 3 Compare/Capture Control Register (0DDh) CCAPM4 - PCA Module 4 Compare/Capture Control Register (0DEh)
7 Bit Number 7 6 ECOMn Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Enable Comparator 6 ECOMn Cleared to disable the comparator function. Set to enable the comparator function. Capture Positive 5 CAPPn Cleared to disable positive edge capture. Set to enable positive edge capture. Capture Negative 4 CAPNn Cleared to disable negative edge capture. Set to enable negative edge capture. Match 3 MATn When MATn = 1, a match of the PCA counter with this Module's compare/capture register causes the CCFn bit in CCON to be set, flagging an interrupt. Toggle 2 TOGn When TOGn = 1, a match of the PCA counter with this Module's compare/capture register causes theCEXn pin to toggle. Pulse Width Modulation Mode 1 PWMn Cleared to disable the CEXn pin to be used as a pulse width modulated output. Set to enable the CEXn pin to be used as a pulse width modulated output. Enable CCF Interrupt 0 CCF0 Cleared to disable compare/capture flag CCFn in the CCON register to generate an interrupt. Set to enable compare/capture flag CCFn in the CCON register to generate an interrupt. 5 CAPPn 4 CAPNn 3 MATn 2 TOGn 1 PWMn 0 ECCFn
Reset Value = X000 0000b Not bit addressable
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Table 25. PCA Module Modes (CCAPMn Registers)
ECOMn 0 X CAPPn 0 1 CAPNn 0 0 MATn 0 0 TOGn 0 0 PWMm 0 0 ECCFn 0 X Module Function No Operation 16-bit capture by a positive-edge trigger on CEXn 16-bit capture by a negative trigger on CEXn 16-bit capture by a transition on CEXn 16-bit Software Timer/Compare mode. 16-bit High-speed Output 8-bit PWM Watchdog Timer (Module 4 only)
X
0
1
0
0
0
X
X
1
1
0
0
0
X
1 1 1 1
0 0 0 0
0 0 0 0
1 1 0 1
0 1 0 X
0 0 1 0
X X 0 X
There are two additional registers associated with each of the PCA Modules. They are CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a Module is used in the PWM mode these registers are used to control the duty cycle of the output (see Table 26 and Table 27). Table 26. CCAPnH Registers (n = 0-4) CCAP0H - PCA Module 0 Compare/Capture Control Register High (0FAh) CCAP1H - PCA Module 1 Compare/Capture Control Register High (0FBh) CCAP2H - PCA Module 2 Compare/Capture Control Register High (0FCh) CCAP3H - PCA Module 3 Compare/Capture Control Register High (0FDh) CCAP4H - PCA Module 4 Compare/Capture Control Register High (0FEh)
7 Bit Number 7-0 6 Bit Mnemonic Description PCA Module n Compare/Capture Control CCAPnH Value 5 4 3 2 1 0 -
Reset Value = 0000 0000b Not bit addressable
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Table 27. CCAPnL Registers (n = 0-4) CCAP0L - PCA Module 0 Compare/Capture Control Register Low (0EAh) CCAP1L - PCA Module 1 Compare/Capture Control Register Low (0EBh) CCAP2L - PCA Module 2 Compare/Capture Control Register Low (0ECh) CCAP3L - PCA Module 3 Compare/Capture Control Register Low (0EDh) CCAP4L - PCA Module 4 Compare/Capture Control Register Low (0EEh)
7 Bit Number 7-0 6 Bit Mnemonic Description PCA Module n Compare/Capture Control CCAPnL Value 5 4 3 2 1 0 -
Reset Value = 0000 0000b Not bit addressable Table 28. CH Register CH - PCA Counter Register High (0F9h)
7 Bit Number 7-0 6 Bit Mnemonic Description PCA Counter CH Value 5 4 3 2 1 0 -
Reset Value = 0000 0000b Not bit addressable Table 29. CL Register CL - PCA Counter Register Low (0E9h)
7 Bit Number 7-0 6 Bit Mnemonic Description PCA Counter CL Value 5 4 3 2 1 0 -
Reset Value = 0000 0000b Not bit addressable
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PCA Capture Mode
To use one of the PCA Modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that Module must be set. The external CEX input for the Module (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the Module's capture registers (CCAPnL and CCAPnH). If the CCFn bit for the Module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated (see Figure 12).
Figure 12. PCA Capture Mode
CF CR CCF4 CCF3 CCF2 CCF1 CCF0 CCON 0xD8 PCA IT
PCA Counter/Timer Cex. n Capture CH CL
CCAPnH
CCAPnL
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n = 0 to 4 0xDA to 0xDE
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16-bit Software Timer/ Compare Mode
The PCA Modules can be used as software timers by setting both the ECOM and MAT bits in the Modules CCAPMn register. The PCA timer will be compared to the Module's capture registers and when a match occurs, an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the Module are both set (see Figure 13).
Figure 13. PCA Compare Mode and PCA Watchdog Timer
CCON CF Write to CCAPnL Write to CCAPnH 1 0 Enable 16 bit Comparator RESET(1) Reset PCA IT CCAPnH CCAPnL Match CR CCF4 CCF3 CCF2 CCF1 CCF0 0xD8
CH
CL
PCA Counter/Timer
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
CCAPMn, n = 0 to 4 0xDA to 0xDE
CIDL
WDTE
CPS1 CPS0
ECF
CMOD 0xD9
Note:
1. Only for Module 4
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could occur. Writing to CCAPnH will set the ECOM bit. Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn't occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this reason, user software should write CCAPnL first, and then CCAPnH. Of course, the ECOM bit can still be controlled by accessing to CCAPMn register.
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High-speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle
each time a match occurs between the PCA counter and the modules capture registers. To activate this mode the TOG, MAT, and ECOM bits in the modules CCAPMn SFR must be set (see Figure 14). A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit. Figure 14. PCA High-speed Output Mode
CCON CF CR CCF4 CCF3 CCF2 CCF1 CCF0 0xD8
Write to CCAPnL Reset
PCA IT Write to CCAPnH 0 CCAPnH Enable 16-bit Comparator CCAPnL Match
1
CH
CL
CEXn
PCA Counter/Timer CCAPMn, n = 0 to 4 0xDA to 0xDE
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non-zero value, otherwise an unwanted match could occur. Once ECOM is set, writing CCAPnL will clear ECOM so that an unwanted match doesn't occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this reason, user software should write CCAPnL first, and then CCAPnH. Of course, the ECOM bit can still be controlled by accessing to CCAPMn register.
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Pulse Width Modulator Mode
All of the PCA Modules can be used as PWM outputs. Figure 15 shows the PWM function. The frequency of the output depends on the source for the PCA timer. All of the Modules will have the same frequency of output because they all share the PCA timer. The duty cycle of each Module is independently variable using the module's capture register CCAPLn. When the value of the PCA CL SFR is less than the value in the module's CCAPLn SFR the output will be low, when it is equal to or greater than the output will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. This allows updating the PWM without glitches. The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode. Figure 15. PCA PWM Mode
CCAPnH Overflow
CCAPnL "0" Enable 8-bit Comparator "1" CL PCA Counter/Timer CEXn
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
CCAPMn, n = 0 to 4 0xDA to 0xDE
PCA Watchdog Timer
An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only PCA Module that can be programmed as a watchdog. However, this Module can still be used for other modes if the watchdog is not needed. Figure 13 shows a diagram of how the watchdog works. The user pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be generated. This will not cause the RST pin to be driven high. In order to hold off the reset, the user has the following three options: 1. Periodically change the compare value so it will never match the PCA timer. 2. Periodically change the PCA timer value so it will never match the compare values. 3. Disable the watchdog by clearing the WDTE bit before a match occurs and then re-enable it. The first two options are more reliable because the watchdog timer is never disabled as in option #3. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. The second option is also not recommended if other PCA Modules are being used. Remember, the PCA timer is the time base for all modules;
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changing the time base for other Modules would not be a good idea. Thus, in most applications the first solution is the best option. This watchdog timer won't generate a reset out on the reset pin.
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Serial I/O Port
The serial I/O port in the AT89C51RB2/RC2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates. Serial I/O port includes the following enhancements: * * Framing error detection Automatic address recognition
Framing Error Detection
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON register (see Figure 16). Figure 16. Framing Error Block Diagram
SM0/FE SM1 SM2 REN TB8 RB8 TI RI SCON (98h)
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1) SM0 to UART mode control (SMOD0 = 0) SMOD1 SMOD0 POF GF1 GF0 PD IDL PCON (87h)
To UART framing error control
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (see Table 33) bit is set. Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (see Figure 17 and Figure 18). Figure 17. UART Timings in Mode 1
RXD Start bit RI SMOD0 = X FE SMOD0 = 1 D0 D1 D2 D3 D4 D5 D6 D7 Stop bit
Data Byte
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Figure 18. UART Timings in Modes 2 and 3
RXD Start bit RI SMOD0 = 0 RI SMOD0 = 1 FE SMOD0 = 1 D0 D1 D2 D3 D4 D5 D6 D7 D8 Ninth Stop bit bit
Data Byte
Automatic Address Recognition
The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU is not interrupted by command frames addressed to other devices. If desired, the user may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the device's address and is terminated by a valid stop bit. To support automatic address recognition, a device is identified by a given address and a broadcast address.
Note: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i. e. setting SM2 bit in SCON register in mode 0 has no effect).
Given Address
Each device has an individual address that is specified in SADDR register; the SADEN register is a mask Byte that contains don't care bits (defined by zeros) to form the device's given address. The don't care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask Byte must be 1111 1111b. For example:
SADDR0101 0110b SADEN1111 1100b Given0101 01XXb
The following is an example of how to use given addresses to address different slaves:
Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 0X0Xb Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 0XX1b Slave C:SADDR1111 0010b SADEN1111 1101b Given1111 00X1b
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The SADEN Byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don't care bit; for slaves B and C, bit 0 is a 1.To communicate with slave A only, the master must send an address where bit 0 is clear (e. g. 1111 0000b). For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don't care bit. To communicate with slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e. g. 1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e. g. 1111 0001b). Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don't care bits, e. g. :
SADDR0101 0110b SADEN1111 1100b Broadcast =SADDR OR SADEN1111 111Xb
The use of don't care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses:
Slave A:SADDR1111 0001b SADEN1111 1010b Broadcast1111 1X11b, Slave B:SADDR1111 0011b SADEN1111 1001b Broadcast1111 1X11B, Slave C:SADDR=1111 0010b SADEN1111 1101b Broadcast1111 1111b
For slaves A and B, bit 2 is a don't care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh. Reset Addresses On reset, the SADDR and SADEN registers are initialized to 00h, i. e. the given and broadcast addresses are XXXX XXXXb (all don't care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition.
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Registers
Table 30. SADEN Register SADEN - Slave Address Mask Register (B9h)
7 6 5 4 3 2 1 0
Reset Value = 0000 0000b Not bit addressable Table 31. SADDR Register SADDR - Slave Address Register (A9h)
7 6 5 4 3 2 1 0
Reset Value = 0000 0000b Not bit addressable
Baud Rate Selection for UART for Mode 1 and 3
The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON registers. Figure 19. Baud Rate Selection
TIMER1 TIMER2 0 1 RCLK INT_BRG RBCK TIMER_BRG_RX 0 1 / 16 Rx Clock
TIMER1 TIMER2
0 1 TCLK
TIMER_BRG_TX 0 1 / 16 Tx Clock
INT_BRG
TBCK
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Table 32. Baud Rate Selection Table UART
TCLK (T2CON) 0 1 0 1 X X 0 1 X RCLK (T2CON) 0 0 1 1 0 1 X X X TBCK (BDRCON) 0 0 0 0 1 1 0 0 1 RBCK (BDRCON) 0 0 0 0 0 0 1 1 1 Clock Source UART Tx Timer 1 Timer 2 Timer 1 Timer 2 INT_BRG INT_BRG Timer 1 Timer 2 INT_BRG Clock Source UART Rx Timer 1 Timer 1 Timer 2 Timer 2 Timer 1 Timer 2 INT_BRG INT_BRG INT_BRG
Internal Baud Rate Generator (BRG)
When the internal Baud Rate Generator is used, the Baud Rates are determined by the BRG overflow depending on the BRL reload value, the value of SPD bit (Speed Mode) in BDRCON register and the value of the SMOD1 bit in PCON register.
Figure 20. Internal Baud Rate
CLK PERIPH /6 0 1 SPD BRR BRL SMOD1 Auto Reload Counter Overflow BRG /2 0 1 INT_BRG
*
The baud rate for UART is token by formula:
Baud_Rate
=
2SMOD1 x FCLK PERIPH
2 x 2 x 6(1-SPD) x 16 x [256 - (BRL)]
(BRL) = 256 -
2SMOD1 x FCLK PERIPH 2 x 2 x 6(1-SPD) x 16 x Baud_Rate
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Table 33. SCON Register SCON - Serial Control Register (98h)
7 FE/SM0 Bit Number 6 SM1 Bit Mnemonic Description Framing Error bit (SMOD0 = 1) FE 7 SM0 Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. SMOD0 must be set to enable access to the FE bit. Serial Port Mode bit 0 see SM1 for serial port mode selection. SMOD0 must be cleared to enable access to the SM0 bit. Serial Port Mode bit 1 SM0 SM1 Mode Description 6 SM1 0 0 1 1 0 1 0 1 0 1 2 3 Shift Register 8-bit UART 9-bit UART 9-bit UART 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI
Baud Rate FCPU PERIPH/6 Variable FCPU PERIPH /32 or /16 Variable
Serial Port Mode 2 bit/Multiprocessor Communication Enable bit 5 SM2 Clear to disable multiprocessor communication feature. Set to enable multiprocessor communication feature in modes 2 and 3, and eventually mode 1.This bit should be cleared in mode 0. Reception Enable bit Clear to disable serial reception. Set to enable serial reception. Transmitter Bit 8/Ninth bit to Transmit in Modes 2 and 3 3 TB8 Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit. Receiver Bit 8/Ninth bit received in Modes 2 and 3 Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used. Transmit Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. Receive Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 17. and Figure 18 in the other modes.
4
REN
2
RB8
1
TI
0
RI
Reset Value = 0000 0000b Bit addressable
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Table 34. Example of Computed Value When X2 = 1, SMOD1 = 1, SPD = 1
Baud Rates FOSC = 16. 384 MHz BRL 115200 57600 38400 28800 19200 9600 4800 247 238 229 220 203 149 43 Error (%) 1.23 1.23 1.23 1.23 0.63 0.31 1.23 BRL 243 230 217 204 178 100 FOSC = 24MHz Error (%) 0.16 0.16 0.16 0.16 0.16 0.16 -
Table 35. Example of Computed Value When X2 = 0, SMOD1 = 0, SPD = 0
Baud Rates FOSC = 16. 384 MHz BRL 4800 2400 1200 600 247 238 220 185 Error (%) 1.23 1.23 1.23 0.16 BRL 243 230 202 152 FOSC = 24MHz Error (%) 0.16 0.16 3.55 0.16
The baud rate generator can be used for mode 1 or 3 (see Figure 19), but also for mode 0 for UART, thanks to the bit SRC located in BDRCON register (Table 42).
UART Registers
Table 36. SADEN Register SADEN - Slave Address Mask Register for UART (B9h)
7 6 5 4 3 2 1 0
Reset Value = 0000 0000b Table 37. SADDR Register SADDR - Slave Address Register for UART (A9h)
7 6 5 4 3 2 1 0
Reset Value = 0000 0000b
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Table 38. SBUF Register SBUF - Serial Buffer Register for UART (99h)
7 6 5 4 3 2 1 0
Reset Value = XXXX XXXXb Table 39. BRL Register BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah)
7 6 5 4 3 2 1 0
Reset Value = 0000 0000b
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Table 40. T2CON Register T2CON - Timer 2 Control Register (C8h)
7 TF2 Bit Number 6 EXF2 Bit Mnemonic Description Timer 2 Overflow Flag Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0. Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2 = 1. When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. Must be cleared by software. EXF2 doesn't cause an interrupt in Up/down counter mode (DCEN = 1) Receive Clock Bit for UART Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3. Transmit Clock Bit for UART Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3. Timer 2 External Enable bit Cleared to ignore events on T2EX pin for timer 2 operation. Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to clock the serial port. Timer 2 Run Control Bit Cleared to turn off timer 2. Set to turn on timer 2. Timer/Counter 2 Select Bit Cleared for timer operation (input from internal clock system: FCLK PERIPH). Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode. Timer 2 Capture/Reload Bit If RCLK = 1 or TCLK = 1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow. Cleared to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2 = 1. Set to capture on negative transitions on T2EX pin if EXEN2 = 1. 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 C/T2# 0 CP/RL2#
7
TF2
6
EXF2
5
RCLK
4
TCLK
3
EXEN2
2
TR2
1
C/T2#
0
CP/RL2#
Reset Value = 0000 0000b Bit addressable
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Table 41. PCON Register PCON - Power Control Register (87h)
7 SMOD1 Bit Number 7 6 SMOD0 Bit Mnemonic SMOD1 Description Serial port Mode Bit 1 for UART Set to select double baud rate in mode 1, 2 or 3. Serial port Mode Bit 0 for UART 6 SMOD0 Cleared to select SM0 bit in SCON register. Set to select FE bit in SCON register. Reserved The value read from this bit is indeterminate. Do not set this bit. Power-off Flag Cleared to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. General-purpose Flag Cleared by user for general-purpose usage. Set by user for general-purpose usage. General-purpose Flag Cleared by user for general-purpose usage. Set by user for general-purpose usage. Power-down Mode Bit Cleared by hardware when reset occurs. Set to enter power-down mode. Idle Mode Bit Cleared by hardware when interrupt or reset occurs. Set to enter idle mode. 5 4 POF 3 GF1 2 GF0 1 PD 0 IDL
5
-
4
POF
3
GF1
2
GF0
1
PD
0
IDL
Reset Value = 00X1 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn't affect the value of this bit.
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Table 42. BDRCON Register BDRCON - Baud Rate Control Register (9Bh)
7 Bit Number 7 6 Bit Mnemonic 5 4 BRR 3 TBCK 2 RBCK 1 SPD 0 SRC
Description Reserved The value read from this bit is indeterminate. Do not set this bit Reserved The value read from this bit is indeterminate. Do not set this bit Reserved The value read from this bit is indeterminate. Do not set this bit. Baud Rate Run Control bit Cleared to stop the internal Baud Rate Generator. Set to start the internal Baud Rate Generator. Transmission Baud rate Generator Selection bit for UART Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator. Set to select internal Baud Rate Generator. Reception Baud Rate Generator Selection bit for UART Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator. Set to select internal Baud Rate Generator. Baud Rate Speed Control bit for UART Cleared to select the SLOW Baud Rate Generator. Set to select the FAST Baud Rate Generator. Baud Rate Source select bit in Mode 0 for UART
6
-
5
-
4
BRR
3
TBCK
2
RBCK
1
SPD
0
SRC
Cleared to select FOSC/12 as the Baud Rate Generator (FCLK PERIPH/6 in X2 mode). Set to select the internal Baud Rate Generator for UARTs in mode 0.
Reset Value = XXX0 0000b Not bit addressablef
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Interrupt System
The AT89C51RB2/RC2 has a total of 9 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Keyboard interrupt and the PCA global interrupt. These interrupts are shown in Figure 21.
Figure 21. Interrupt Control System
IPH, IPL 3 INT0 IE0 0 3 TF0 0 3 INT1 IE1 0 3 TF1 0 3 PCA IT 0 RI TI 3 0 3 0 3 KBD IT 0 3 SPI IT 0 Interrupt Polling Sequence, Decreasing From High to Low Priority High Priority Interrupt
TF2 EXF2
Individual Enable
Global Disable
Low Priority Interrupt
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register (Table 45 and Table 47). This register also contains a global disable bit, which must be cleared to disable all interrupts at once. Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the Interrupt Priority register (Table 48) and in the Interrupt Priority High register (Table 46 and Table 47) shows the bit values and priority levels associated with each combination.
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Registers
A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can't be interrupted by any other interrupt source. Table 43. Priority Level Bit Values
IPH. x 0 0 1 1 IPL. x 0 1 0 1 Interrupt Level Priority 0 (Lowest) 1 2 3 (Highest)
If two interrupt requests of different priority levels are received simultaneously, the request of higher-priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence.
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Table 44. IENO Register IEN0 - Interrupt Enable Register (A8h)
7 EA Bit Number 6 EC Bit Mnemonic Description Enable All Interrupt Bit Cleared to disable all interrupts. Set to enable all interrupts. PCA Interrupt Enable Bit 6 EC Cleared to disable. Set to enable. Timer 2 Overflow Interrupt Enable Bit Cleared to disable timer 2 overflow interrupt. Set to enable timer 2 overflow interrupt. Serial Port Enable Bit Cleared to disable serial port interrupt. Set to enable serial port interrupt. Timer 1 Overflow Interrupt Enable Bit Cleared to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt. External Interrupt 1 Enable Bit Cleared to disable external interrupt 1. Set to enable external interrupt 1. Timer 0 Overflow Interrupt Enable Bit Cleared to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. External Interrupt 0 Enable Bit Cleared to disable external interrupt 0. Set to enable external interrupt 0. 5 ET2 4 ES 3 ET1 2 EX1 1 ET0 0 EX0
7
EA
5
ET2
4
ES
3
ET1
2
EX1
1
ET0
0
EX0
Reset Value = 0000 0000b Bit addressable
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Table 45. IPL0 Register IPL0 - Interrupt Priority Register (B8h)
7 Bit Number 7 6 PPCL Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. PCA Interrupt Priority Bit see PPCH for priority level. Timer 2 Overflow Interrupt Priority Bit see PT2H for priority level. Serial Port Priority Bit see PSH for priority level. Timer 1 Overflow Interrupt Priority Bit see PT1H for priority level. External Interrupt 1 Priority Bit see PX1H for priority level. Timer 0 Overflow Interrupt Priority Bit see PT0H for priority level. External Interrupt 0 Priority Bit see PX0H for priority level. 5 PT2L 4 PSL 3 PT1L 2 PX1L 1 PT0L 0 PX0L
6
PPCL
5
PT2L
4
PSL
3
PT1L
2
PX1L
1
PT0L
0
PX0L
Reset Value = X000 0000b Bit addressable
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Table 46. IPH0 Register IPH0 - Interrupt Priority High Register (B7h)
7 Bit Number 7 6 PPCH Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. PCA Interrupt Priority High Bit PPCH PPCL Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Timer 2 Overflow Interrupt Priority High Bit PT2L Priority Level PT2H 0 0 Lowest 0 1 1 0 1 1 Highest Serial Port Priority High Bit PSH PSL Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Timer 1 Overflow Interrupt Priority High Bit PT1L Priority Level PT1H 0 0 Lowest 0 1 1 0 1 1 Highest External Interrupt 1 Priority High Bit PX1L Priority Level PX1H 0 0 Lowest 0 1 1 0 1 1 Highest Timer 0 Overflow Interrupt Priority High Bit PT0H PT0L Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest External Interrupt 0 Priority High Bit PX0L Priority Level PX0H 0 0 Lowest 0 1 1 0 1 1 Highest 5 PT2H 4 PSH 3 PT1H 2 PX1H 1 PT0H 0 PX0H
6
PPCH
5
PT2H
4
PSH
3
PT1H
2
PX1H
1
PT0H
0
PX0H
Reset Value = X000 0000b Not bit addressable
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Table 47. IEN1 Register IEN1 - Interrupt Enable Register (B1h)
7 Bit Number 7 6 5 4 3 6 Bit Mnemonic Description Reserved Reserved Reserved Reserved Reserved SPI Interrupt Enable Bit Cleared to disable SPI interrupt. Set to enable SPI interrupt. 1 Reserved Keyboard Interrupt Enable Bit Cleared to disable keyboard interrupt. Set to enable keyboard interrupt. 5 4 3 2 SPI 1 0 KBD
2
SPI
0
KBD
Reset Value = XXXX X000b Bit addressable
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Table 48. IPL1 Register IPL1 - Interrupt Priority Register (B2h)
7 Bit Number 7 6 Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. SPI Interrupt Priority Bit see SPIH for priority level. Reserved The value read from this bit is indeterminate. Do not set this bit. Keyboard Interrupt Priority Bit see KBDH for priority level. 5 4 3 2 SPIL 1 0 KBDL
6
-
5
-
4
-
3
-
2
SPIL
1
-
0
KBDL
Reset Value = XXXX X000b Bit addressable
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Table 49. IPH1 Register IPH1 - Interrupt Priority High Register (B3h)
7 Bit Number 7 6 Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. SPI Interrupt Priority High Bit SPIH SPIL Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Reserved The value read from this bit is indeterminate. Do not set this bit. Keyboard Interrupt Priority High Bit KB DH KBDL Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest 5 4 3 2 SPIH 1 0 KBDH
6
-
5
-
4
-
3
-
2
SPIH
1
-
0
KBDH
Reset Value = XXXX X000b Not bit addressable
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Interrupt Sources and Vector Addresses
Table 50. Interrupt Sources and Vector Addresses
Number 0 1 2 3 4 5 6 7 8 9 Polling Priority 0 1 2 3 4 6 7 5 8 9 Interrupt Source Reset INT0 Timer 0 INT1 Timer 1 UART Timer 2 PCA Keyboard SPI IE0 TF0 IE1 IF1 RI+TI TF2+EXF2 CF + CCFn (n = 0-4) KBDIT SPIIT Interrupt Request Vector Address 0000h 0003h 000Bh 0013h 001Bh 0023h 002Bh 0033h 003Bh 004Bh
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Keyboard Interface
The AT89C51RB2/RC2 implements a keyboard interface allowing the connection of a 8 x n matrix keyboard. It is based on 8 inputs with programmable interrupt capability on both high or low level. These inputs are available as alternate function of P1 and allow to exit from idle and power-down modes. The keyboard interfaces with the C51 core through 3 special function registers: KBLS, the Keyboard Level Selection register (Table 53), KBE, the Keyboard interrupt Enable register (Table 52), and KBF, the Keyboard Flag register (Table 51).
Interrupt
The keyboard inputs are considered as 8 independent interrupt sources sharing the same interrupt vector. An interrupt enable bit (KBD in IEN1) allows global enable or disable of the keyboard interrupt (see Figure 22). As detailed in Figure 23 each keyboard input has the capability to detect a programmable level according to KBLS. x bit value. Level detection is then reported in interrupt flags KBF. x that can be masked by software using KBE. x bits. This structure allows keyboard arrangement from 1 by n to 8 by n matrix and allow usage of P1 inputs for other purpose. Figure 22. Keyboard Interface Block Diagram
VCC
0
P1:x
1
Internal Pull-up
KBF. x KBE. x KBLS. x
Figure 23. Keyboard Input Circuitry
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 Input Circuitry Input Circuitry Input Circuitry Input Circuitry KBDIT Input Circuitry Input Circuitry Input Circuitry Input Circuitry KBD IEN1 Keyboard Interface Interrupt Request
Power Reduction Mode
P1 inputs allow exit from idle and power down modes as detailed in Section "Powerdown Mode", page 80.
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Registers
Table 51. KBF Register KBF - Keyboard Flag Register (9Eh)
7 KBF7 Bit Number 6 KBF6 5 KBF5 4 KBF4 3 KBF3 2 KBF2 1 KBF1 0 KBF0
Bit Mnemonic Description Keyboard Line 7 Flag Set by hardware when the Port line 7 detects a programmed level. It generates a Keyboard interrupt request if the KBKBIE. 7 bit in KBIE register is set. Must be cleared by software. Keyboard Line 6 Flag Set by hardware when the Port line 6 detects a programmed level. It generates a Keyboard interrupt request if the KBIE. 6 bit in KBIE register is set. Must be cleared by software. Keyboard Line 5 Flag Set by hardware when the Port line 5 detects a programmed level. It generates a Keyboard interrupt request if the KBIE. 5 bit in KBIE register is set. Must be cleared by software. Keyboard Line 4 Flag Set by hardware when the Port line 4 detects a programmed level. It generates a Keyboard interrupt request if the KBIE. 4 bit in KBIE register is set. Must be cleared by software. Keyboard Line 3 Flag Set by hardware when the Port line 3 detects a programmed level. It generates a Keyboard interrupt request if the KBIE. 3 bit in KBIE register is set. Must be cleared by software. Keyboard Line 2 Flag Set by hardware when the Port line 2 detects a programmed level. It generates a Keyboard interrupt request if the KBIE. 2 bit in KBIE register is set. Must be cleared by software. Keyboard Line 1 Flag Set by hardware when the Port line 1 detects a programmed level. It generates a Keyboard interrupt request if the KBIE. 1 bit in KBIE register is set. Must be cleared by software. Keyboard Line 0 Flag Set by hardware when the Port line 0 detects a programmed level. It generates a Keyboard interrupt request if the KBIE. 0 bit in KBIE register is set. Must be cleared by software.
7
KBF7
6
KBF6
5
KBF5
4
KBF4
3
KBF3
2
KBF2
1
KBF1
0
KBF0
Reset Value = 0000 0000b
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Table 52. KBE Register KBE - Keyboard Input Enable Register (9Dh)
7 KBE7 Bit Number 6 KBE6 5 KBE5 4 KBE4 3 KBE3 2 KBE2 1 KBE1 0 KBE0
Bit Mnemonic Description Keyboard Line 7 Enable Bit Cleared to enable standard I/O pin. Set to enable KBF. 7 bit in KBF register to generate an interrupt request. Keyboard Line 6 Enable Bit Cleared to enable standard I/O pin. Set to enable KBF. 6 bit in KBF register to generate an interrupt request. Keyboard Line 5 Enable Bit Cleared to enable standard I/O pin. Set to enable KBF. 5 bit in KBF register to generate an interrupt request. Keyboard Line 4 Enable Bit Cleared to enable standard I/O pin. Set to enable KBF. 4 bit in KBF register to generate an interrupt request. Keyboard Line 3 Enable Bit Cleared to enable standard I/O pin. Set to enable KBF. 3 bit in KBF register to generate an interrupt request. Keyboard Line 2 Enable Bit Cleared to enable standard I/O pin. Set to enable KBF. 2 bit in KBF register to generate an interrupt request. Keyboard Line 1 Enable Bit Cleared to enable standard I/O pin. Set to enable KBF. 1 bit in KBF register to generate an interrupt request. Keyboard Line 0 Enable Bit Cleared to enable standard I/O pin. Set to enable KBF. 0 bit in KBF register to generate an interrupt request.
7
KBE7
6
KBE6
5
KBE5
4
KBE4
3
KBE3
2
KBE2
1
KBE1
0
KBE0
Reset Value = 0000 0000b
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Table 53. KBLS Register KBLS - Keyboard Level Selector Register (9Ch)
7 KBLS7 Bit Number 6 KBLS6 5 KBLS5 4 KBLS4 3 KBLS3 2 KBLS2 1 KBLS1 0 KBLS0
Bit Mnemonic Description Keyboard Line 7 Level Selection Bit Cleared to enable a low level detection on Port line 7. Set to enable a high level detection on Port line 7. Keyboard Line 6 Level Selection Bit Cleared to enable a low level detection on Port line 6. Set to enable a high level detection on Port line 6. Keyboard Line 5 Level Selection Bit Cleared to enable a low level detection on Port line 5. Set to enable a high level detection on Port line 5. Keyboard Line 4 Level Selection Bit Cleared to enable a low level detection on Port line 4. Set to enable a high level detection on Port line 4. Keyboard Line 3 Level Selection Bit Cleared to enable a low level detection on Port line 3. Set to enable a high level detection on Port line 3. Keyboard Line 2 Level Selection Bit Cleared to enable a low level detection on Port line 2. Set to enable a high level detection on Port line 2. Keyboard Line 1 Level Selection Bit Cleared to enable a low level detection on Port line 1. Set to enable a high level detection on Port line 1. Keyboard Line 0 Level Selection Bit Cleared to enable a low level detection on Port line 0. Set to enable a high level detection on Port line 0.
7
KBLS7
6
KBLS6
5
KBLS5
4
KBLS4
3
KBLS3
2
KBLS2
1
KBLS1
0
KBLS0
Reset Value = 0000 0000b
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Serial Port Interface (SPI)
Features
The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. Features of the SPI Module include the following: * * * * * * Full-duplex, three-wire synchronous transfers Master or Slave operation Eight programmable Master clock rates Serial clock with programmable polarity and phase Master Mode fault error flag with MCU interrupt capability Write collision flag protection
Signal Description
Figure 24 shows a typical SPI bus configuration using one Master controller and many Slave peripherals. The bus is made of three wires connecting all the devices. Figure 24. SPI Master/Slaves Interconnection
MISO MOSI SCK SS
Slave 1
MISO MOSI SCK SS
VDD
Master
0 1 2 3
PORT
Slave 4
MISO MOSI SCK SS
Slave 3
MISO MOSI SCK SS
Slave 2
The Master device selects the individual Slave devices by using four pins of a parallel port to control the four SS pins of the Slave devices. Master Output Slave Input (MOSI) This 1-bit signal is directly connected between the Master Device and a Slave Device. The MOSI line is used to transfer data in series from the Master to the Slave. Therefore, it is an output signal from the Master, and an input signal to a Slave. A Byte (8-bit word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last. This 1-bit signal is directly connected between the Slave Device and a Master Device. The MISO line is used to transfer data in series from the Slave to the Master. Therefore, it is an output signal from the Slave, and an input signal to the Master. A Byte (8-bit word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last. This signal is used to synchronize the data movement both in and out of the devices through their MOSI and MISO lines. It is driven by the Master for eight clock cycles which allows to exchange one Byte on the serial lines. Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay low for any message for a Slave. It is obvious that only one Master (SS high level) can
Master Input Slave Output (MISO)
SPI Serial Clock (SCK)
Slave Select (SS)
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MISO MOSI SCK SS
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drive the network. The Master may select each Slave device by software through port pins (Figure 25). To prevent bus conflicts on the MISO line, only one slave should be selected at a time by the Master for a transmission. In a Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and SCK (see Error conditions). A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state. The SS pin could be used as a general-purpose if the following conditions are met: * The device is configured as a Master and the SSDIS control bit in SPCON is set. This kind of configuration can be found when only one Master is driving the network and there is no way that the SS pin could be pulled low. Therefore, the MODF flag in the SPSTA will never be set(1). The Device is configured as a Slave with CPHA and SSDIS control bits set(2). This kind of configuration can happen when the system comprises one Master and one Slave only. Therefore, the device should always be selected and there is no reason that the Master uses the SS pin to select the communicating Slave device.
1. Clearing SSDIS control bit does not clear MODF. 2. Special care should be taken not to set SSDIS control bit when CPHA = '0' because in this mode, the SS is used to start the transmission.
*
Note:
Baud Rate
In Master mode, the baud rate can be selected from a baud rate generator which is controlled by three bits in the SPCON register: SPR2, SPR1 and SPR0.The Master clock is selected from one of seven clock rates resulting from the division of the internal clock by 2, 4, 8, 16, 32, 64 or 128. Table 54 gives the different clock rates selected by SPR2:SPR1:SPR0. Table 54. SPI Master Baud Rate Selection
SPR2 0 0 0 0 1 1 1 1 SPR1 0 0 1 1 0 0 1 1 SPR0 0 1 0 1 0 1 0 1 Clock Rate Don't Use FCLK PERIPH /4 FCLK PERIPH/8 FCLK PERIPH /16 FCLK PERIPH /32 FCLK PERIPH /64 FCLK PERIPH /128 Don't Use Baud Rate Divisor (BD) No BRG 4 8 16 32 64 128 No BRG
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Functional Description
Figure 25 shows a detailed structure of the SPI Module. Figure 25. SPI Module Block Diagram
Internal Bus SPDAT
FCLK PERIPH
Shift Register
7 6 5 4 3 2 1 0
Clock Divider
/4 /8 /16 /32 /64 /128
Receive Data Register
Pin Control Logic
MOSI MISO
Clock Logic Clock Select
M S
SCK SS
SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
SPCON
SPI Control
8-bit bus 1-bit signal
SPI Interrupt Request
SPSTA
SPIF WCOL MODF -
Operating Modes
The Serial Peripheral Interface can be configured in one of the two modes: Master mode or Slave mode. The configuration and initialization of the SPI Module is made through one register: * * * * The Serial Peripheral Control register (SPCON) SPCON The Serial Peripheral STAtus register (SPSTA) The Serial Peripheral DATa register (SPDAT) Once the SPI is configured, the data exchange is made using:
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sampling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows individual selection of a Slave SPI device; Slave devices that are not selected do not interfere with SPI bus activities. When the Master device transmits data to the Slave device via the MOSI line, the Slave device responds by sending data to the Master device via the MISO line. This implies full-duplex transmission with both data out and data in synchronized with the same clock (Figure 26).
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Figure 26. Full-Duplex Master-Slave Interconnection
MISO MOSI SPI Clock Generator SCK SS VDD MISO MOSI SCK SS VSS
8-bit Shift register
8-bit Shift register
Master MCU
Slave MCU
Master Mode
The SPI operates in Master mode when the Master bit, MSTR (1), in the SPCON register is set. Only one Master SPI device can initiate transmissions. Software begins the transmission from a Master SPI Module by writing to the Serial Peripheral Data Register (SPDAT). If the shift register is empty, the Byte is immediately transferred to the shift register. The Byte begins shifting out on MOSI pin under the control of the serial clock, SCK. Simultaneously, another Byte shifts in from the Slave on the Master's MISO pin. The transmission ends when the Serial Peripheral transfer data flag, SPIF, in SPSTA becomes set. At the same time that SPIF becomes set, the received Byte from the Slave is transferred to the receive data register in SPDAT. Software clears SPIF by reading the Serial Peripheral Status register (SPSTA) with the SPIF bit set, and then reading the SPDAT. The SPI operates in Slave mode when the Master bit, MSTR (2), in the SPCON register is cleared. Before a data transmission occurs, the Slave Select pin, SS, of the Slave device must be set to '0'. SS must remain low until the transmission is complete. In a Slave SPI Module, data enters the shift register under the control of the SCK from the Master SPI Module. After a Byte enters the shift register, it is immediately transferred to the receive data register in SPDAT, and the SPIF bit is set. To prevent an overflow condition, Slave software must then read the SPDAT before another Byte enters the shift register (3). A Slave SPI must complete the write to the SPDAT (shift register) at least one bus cycle before the Master SPI starts a transmission. If the write to the data register is late, the SPI transmits the data already in the shift register from the previous transmission.
Slave Mode
Transmission Formats
Software can select any of four combinations of serial clock (SCK) phase and polarity using two bits in the SPCON: the Clock Polarity (CPOL (4) ) and the Clock Phase (CPHA4). CPOL defines the default SCK line level in idle state. It has no significant effect on the transmission format. CPHA defines the edges on which the input data are sampled and the edges on which the output data are shifted (Figure 22 and Figure 23). The clock phase and polarity should be identical for the Master SPI device and the communicating Slave device.
1. 2. 3. 4.
The SPI Module should be configured as a Master before it is enabled (SPEN set). Also, the Master SPI should be configured before the Slave SPI. The SPI Module should be configured as a Slave before it is enabled (SPEN set). The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock speed. Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = '0').
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Figure 27. Data Transmission Format (CPHA = 0)
SCK Cycle Number SPEN (Internal)
1 2 3 4 5 6 7 8
SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) SS (to Slave) Capture Point
MSB MSB bit6 bit6 bit5 bit5 bit4 bit4 bit3 bit3 bit2 bit2 bit1 bit1 LSB LSB
Figure 28. Data Transmission Format (CPHA = 1)
SCK Cycle Number SPEN (Internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) SS (to Slave) Capture Point
MSB MSB bit6 bit6 bit5 bit5 bit4 bit4 bit3 bit3 bit2 bit2 bit1 bit1 LSB LSB 1 2 3 4 5 6 7 8
Figure 29. CPHA/SS Timing
MISO/MOSI Master SS Slave SS (CPHA = 0) Slave SS (CPHA = 1) Byte 1 Byte 2 Byte 3
As shown in Figure 27, the first SCK edge is the MSB capture strobe. Therefore, the Slave must begin driving its data before the first SCK edge, and a falling edge on the SS pin is used to start the transmission. The SS pin must be toggled high and then low between each Byte transmitted (Figure 29). Figure 28 shows an SPI transmission in which CPHA is '1'. In this case, the Master begins driving its MOSI pin on the first SCK edge. Therefore, the Slave uses the first SCK edge as a start transmission signal. The SS pin can remain low between transmissions (Figure 29). This format may be preffered in systems having only one Master and only one Slave driving the MISO data line.
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Error Conditions Mode Fault (MODF) The following flags in the SPSTA signal SPI error conditions: Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with the actual mode of the device. MODF is set to warn that there may be a multi-master conflict for system control. In this case, the SPI system is affected in the following ways: * * * An SPI receiver/error CPU interrupt request is generated The SPEN bit in SPCON is cleared. This disables the SPI The MSTR bit in SPCON is cleared
When SS Disable (SSDIS) bit in the SPCON register is cleared, the MODF flag is set when the SS signal becomes '0'. However, as stated before, for a system with one Master, if the SS pin of the Master device is pulled low, there is no way that another Master attempts to drive the network. In this case, to prevent the MODF flag from being set, software can set the SSDIS bit in the SPCON register and therefore making the SS pin as a general-purpose I/O pin. Clearing the MODF bit is accomplished by a read of SPSTA register with MODF bit set, followed by a write to the SPCON register. SPEN Control bit may be restored to its original set state after the MODF bit has been cleared. Write Collision (WCOL) A Write Collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is done during a transmit sequence. WCOL does not cause an interruption, and the transfer continues uninterrupted. Clearing the WCOL bit is done through a software sequence of an access to SPSTA and an access to SPDAT. Overrun Condition An overrun condition occurs when the Master device tries to send several data Bytes and the Slave devise has not cleared the SPIF bit issuing from the previous data Byte transmitted. In this case, the receiver buffer contains the Byte sent after the SPIF bit was last cleared. A read of the SPDAT returns this Byte. All others Bytes are lost. This condition is not detected by the SPI peripheral. SS Error Flag (SSERR) A Synchronous Serial Slave Error occurs when SS goes high before the end of a received data in slave mode. SSERR does not cause in interruption, this bit is cleared by writing 0 to SPEN bit (reset of the SPI state machine). Two SPI status flags can generate a CPU interrupt requests: Table 55. SPI Interrupts
Flag SPIF (SP data transfer) MODF (Mode Fault) Request SPI Transmitter Interrupt request SPI Receiver/Error Interrupt Request (if SSDIS = '0')
Interrupts
Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer has been completed. SPIF bit generates transmitter CPU interrupt requests. Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is inconsistent with the mode of the SPI. MODF with SSDIS reset, generates receiver/error CPU interrupt requests. When SSDIS is set, no MODF interrupt request is generated. Figure 30 gives a logical view of the above statements. 71
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Figure 30. SPI Interrupt Requests Generation
SPIF SPI Transmitter CPU Interrupt Request SPI Receiver/error CPU Interrupt Request SSDIS SPI CPU Interrupt Request
MODF
Registers Serial Peripheral Control Register (SPCON)
There are three registers in the Module that provide control, status and data storage functions. These registers are describes in the following paragraphs.
* * * * * *
The Serial Peripheral Control Register does the following: Selects one of the Master clock rates Configure the SPI Module as Master or Slave Selects serial clock polarity and phase Enables the SPI Module Frees the SS pin for a general-purpose
Table 56 describes this register and explains the use of each bit Table 56. SPCON Register SPCON - Serial Peripheral Control Register (0C3H)
7 SPR2 Bit Number 7 6 SPEN 5 SSDIS 4 MSTR Description Serial Peripheral Rate 2 Bit with SPR1 and SPR0 define the clock rate. Serial Peripheral Enable 6 SPEN Cleared to disable the SPI interface. Set to enable the SPI interface. SS Disable Cleared to enable SS in both Master and Slave modes. 5 SSDIS Set to disable SS in both Master and Slave modes. In Slave mode, this bit has no effect if CPHA ='0'. When SSDIS is set, no MODF interrupt request is generated. Serial Peripheral Master 5 MSTR Cleared to configure the SPI as a Slave. Set to configure the SPI as a Master. Clock Polarity 4 CPOL Cleared to have the SCK set to '0' in idle state. Set to have the SCK set to '1' in idle low. Clock Phase 3 CPHA Cleared to have the data sampled when the SCK leaves the idle state (see CPOL). Set to have the data sampled when the SCK returns to idle state (see CPOL). 3 CPOL 2 CPHA 1 SPR1 0 SPR0
Bit Mnemonic SPR2
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Bit Number Bit Mnemonic Description SPR2 2 SPR1 0 0 0 0 1 1 SPR0 1 1 1 SPR1 0 0 1 1 0 0 1 1 SPR0 Serial Peripheral Rate 0 1 0 1 0 1 0 1 Invalid FCLK PERIPH /4 FCLK PERIPH /8 FCLK PERIPH /16 FCLK PERIPH /32 FCLK PERIPH /64 FCLK PERIPH /128 Invalid
Reset Value = 0001 0100b Not bit addressable Serial Peripheral Status Register (SPSTA) The Serial Peripheral Status Register contains flags to signal the following conditions: * * * Data transfer complete Write collision Inconsistent logic level on SS pin (mode fault error)
Table 57 describes the SPSTA register and explains the use of every bit in the register. Table 57. SPSTA Register SPSTA - Serial Peripheral Status and Control register (0C4H)
7 SPIF Bit Number 6 WCOL 5 SSERR 4 MODF 3 2 1 0 -
Bit Mnemonic Description Serial Peripheral Data Transfer Flag
7
SPIF
Cleared by hardware to indicate data transfer is in progress or has been approved by a clearing sequence. Set by hardware to indicate that the data transfer has been completed. Write Collision Flag
6
WCOL
Cleared by hardware to indicate that no collision has occurred or has been approved by a clearing sequence. Set by hardware to indicate that a collision has been detected. Synchronous Serial Slave Error Flag
5
SSERR
Set by hardware when SS is deasserted before the end of a received data. Cleared by disabling the SPI (clearing SPEN bit in SPCON). Mode Fault
4
MODF
Cleared by hardware to indicate that the SS pin is at appropriate logic level, or has been approved by a clearing sequence. Set by hardware to indicate that the SS pin is at inappropriate logic level.
3
-
Reserved The value read from this bit is indeterminate. Do not set this bit Reserved The value read from this bit is indeterminate. Do not set this bit.
2
-
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Bit Number 1
Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit.
0
-
Reset Value = 00X0 XXXXb Not Bit addressable Serial Peripheral DATa Register (SPDAT) The Serial Peripheral Data Register (Table 58) is a read/write buffer for the receive data register. A write to SPDAT places data directly into the shift register. No transmit buffer is available in this model. A Read of the SPDAT returns the value located in the receive buffer and not the content of the shift register. Table 58. SPDAT Register SPDAT - Serial Peripheral Data Register (0C5H)
7 R7 6 R6 5 R5 4 R4 3 R3 2 R2 1 R1 0 R0
Reset Value = Indeterminate R7:R0: Receive data bits SPCON, SPSTA and SPDAT registers may be read and written at any time while there is no on-going exchange. However, special care should be taken when writing to them while a transmission is on-going: * * * * * Do not change SPR2, SPR1 and SPR0 Do not change CPHA and CPOL Do not change MSTR Clearing SPEN would immediately disable the peripheral Writing to the SPDAT will cause an overflow.
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AT89C51RB2/RC2
Hardware Watchdog Timer
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST-pin. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST-pin. The RESET pulse duration is 96 x TCLK PERIPH, where TCLK PERIPH= 1/FCLK PERIPH. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset. To have a more powerful WDT, a 27 counter has been added to extend the Time-out capability, ranking from 16 ms to 2 s @ FOSCA = 12 MHz. To manage this feature, see WDTPRG register description, Table 59. Table 59. WDTRST Register WDTRST - Watchdog Reset Register (0A6h)
7 6 5 4 3 2 1 0 -
Using the WDT
Reset Value = XXXX XXXXb Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence.
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Table 60. WDTPRG Register WDTPRG - Watchdog Timer Out Register (0A7h)
7 Bit Number 7 6 5 4 3 2 1 0 6 Bit Mnemonic Description S2 S1 S0 WDT Time-out Select Bit 2 WDT Time-out Select Bit 1 WDT Time-out Select Bit 0 S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Selected Time-out (214 - 1) machine cycles, 16. 3 ms @ FOSCA = 12 MHz (215 - 1) machine cycles, 32.7 ms @ FOSCA = 12 MHz (216 - 1) machine cycles, 65. 5 ms @ FOSCA = 12 MHz (217 - 1) machine cycles, 131 ms @ FOSCA = 12 MHz (218 - 1) machine cycles, 262 ms @ FOSCA = 12 MHz (219 - 1) machine cycles, 542 ms @ FOSCA = 12 MHz (220 - 1) machine cycles, 1.05 s @ FOSCA = 12 MHz (221 - 1) machine cycles, 2.09 s @ FOSCA = 12 MHz Reserved The value read from this bit is undetermined. Do not try to set this bit. 5 4 3 2 S2 1 S1 0 S0
Reset Value = XXXX X000
WDT During Power-down In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode the user does not need to service the WDT. There are two methods and Idle
of exiting Power-down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally should whenever the AT89C51RB2/RC2 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service routine. To ensure that the WDT does not overflow within a few states of exiting of power-down, it is better to reset the WDT just before entering power-down. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the AT89C51RB2/RC2 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode.
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ONCETM Mode (ON Chip Emulation)
The ONCE mode facilitates testing and debugging of systems using AT89C51RB2/RC2 without removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the AT89C51RB2/RC2; the following sequence must be exercised: * * Pull ALE low while the device is in reset (RST high) and PSEN is high. Hold ALE low as RST is deactivated.
While the AT89C51RB2/RC2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit. Table 61 shows the status of the port pins during ONCE mode. Normal operation is restored when normal reset is applied. Table 61. External Pin Status during ONCE Mode
ALE Weak pull-up PSEN Weak pull-up Port 0 Float Port 1 Weak pull-up Port 2 Weak pull-up Port 3 Weak pull-up XTAL1/2 Active
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Power Management
Two power reduction modes are implemented in the AT89C51RB2/RC2: the Idle mode and the Power-down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2 using the X2 mode detailed in Section "X2 Feature". In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, an high level has to be applied on the RST pin. A bad level leads to a wrong initialization of the internal registers like SFRs, Program Counter... and to unpredictable behavior of the microcontroller. A proper device reset initializes the AT89C51RB2/RC2 and vectors the CPU to address 0000h. RST input has a pull-down resistor allowing power-on reset by simply connecting an external capacitor to VDD as shown in Figure 31. A warm reset can be applied either directly on the RST pin or indirectly by an internal reset source such as the watchdog timer. Resistor value and input characteristics are discussed in the Section "DC Characteristics" of the AT89C51RB2/RC2 datasheet. Figure 31. Reset Circuitry and Power-On Reset
VDD
Reset
From Internal Reset Source To CPU Core and Peripherals
VDD
P
RST
RRST
+
RST
VSS
RST input circuitry
Power-on Reset
Cold Reset
2 conditions are required before enabling a CPU start-up: * * VDD must reach the specified VDD range The level on X1 input pin must be outside the specification (VIH, VIL)
If one of these 2 conditions are not met, the microcontroller does not start correctly and can execute an instruction fetch from anywhere in the program space. An active level applied on the RST pin must be maintained till both of the above conditions are met. A reset is active when the level V IH1 is reached and when the pulse width covers the period of time where VDD and the oscillator are not stabilized. 2 parameters have to be taken into account to determine the reset pulse width: * * VDD rise time, Oscillator startup time.
To determine the capacitor value to implement, the highest value of these 2 parameters has to be chosen. Table 1 gives some capacitor values examples for a minimum RRST of 50 K and different oscillator startup and VDD rise times.
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Table 1. Minimum Reset Capacitor Value for a 50 k Pull-down Resistor(1)
Oscillator Start-Up Time 5 ms 20 ms Note: VDD Rise Time 1 ms 820 nF 2.7 F 10 ms 1.2 F 3.9 F 100 ms 12 F 12 F
These values assume VDD starts from 0V to the nominal value. If the time between 2 on/off sequences is too fast, the power-supply de-coupling capacitors may not be fully discharged, leading to a bad reset sequence.
Warm Reset
To achieve a valid reset, the reset signal must be maintained for at least 2 machine cycles (24 oscillator clock periods) while the oscillator is running. The number of clock periods is mode independent (X2 or X1). As detailed in Section "Watchdog Timer", page 59, the WDT generates a 96-clock period pulse on the RST pin. In order to properly propagate this pulse to the rest of the application in case of external capacitor or power-supply supervisor circuit, a 1 k resistor must be added as shown Figure 32. Figure 32. Reset Circuitry for WDT Reset-out Usage
VDD
Watchdog Reset
+
VDD
From WDT Reset Source To CPU Core and Peripherals
RST
VDD
1K
P
RST
RRST
VSS
VSS
To Other On-board Circuitry
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Reset Recommendation to Prevent Flash Corruption
An example of bad initialization situation may occur in an instance where the bit ENBOOT in AUXR1 register is initialized from the hardware bit BLJB upon reset. Since this bit allows mapping of the bootloader in the code area, a reset failure can be critical. If one wants the ENBOOT cleared in order to unmap the boot from the code area (yet due to a bad reset) the bit ENBOOT in SFRs may be set. If the value of Program Counter is accidently in the range of the boot memory addresses then a Flash access (write or erase) may corrupt the Flash on-chip memory. It is recommended to use an external reset circuitry featuring power supply monitoring to prevent system malfunction during periods of insufficient power supply voltage (power supply failure, power supply switched off).
Idle Mode
An instruction that sets PCON.0 indicates that it is the last instruction to be executed before going into Idle mode. In Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator and all other registers maintain their data during idle. The port pins hold the logical states they had at the time Idle was activated. ALE and PSEN hold at logic high level. There are two ways to terminate the Idle mode. Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be serviced, and following RETI the next instruction to be executed will be the one following the instruction that put the device into idle. The flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred during normal operation or during idle. For example, an instruction that activates idle can also set one or both flag bits. When idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is still running, the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset.
Power-down Mode
To save maximum power, a Power-down mode can be invoked by software (see Table 14, PCON register). In Power-down mode, the oscillator is stopped and the instruction that invoked Powerdown mode is the last instruction executed. The internal RAM and SFRs retain their value until the Power-down mode is terminated. VCC can be lowered to save further power. Either a hardware reset or an external interrupt can cause an exit from Powerdown. To properly terminate Power-down, the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize. Only external interrupts INT0, INT1 and Keyboard Interrupts are useful to exit from Power-down. For that, interrupt must be enabled and configured as level or edge sensitive interrupt input. When Keyboard Interrupt occurs after a power down mode, 1024 clocks are necessary to exit to power down mode and enter in operating mode. Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 33. When both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and power down exit will be completed when the first input will be released. In this case, the higher priority interrupt service routine is executed. Once the interrupt is serviced, the next instruction to be executed after RETI will
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be the one following the instruction that puts the AT89C51RB2/RC2 into Power-down mode. Figure 33. Power-down Exit Waveform
INT0 INT1
XTALA or XTALB
Active Phase Power-down Phase Oscillator Restart Phase Active Phase
Exit from Power-down by reset redefines all the SFRs, exit from Power-down by external interrupt does no affect the SFRs. Exit from Power-down by either reset or external interrupt does not affect the internal RAM content.
Note: If idle mode is activated with Power-down mode (IDL and PD bits set), the exit sequence is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and idle mode is not entered.
Table 62 shows the state of ports during idle and power-down modes.
Table 62. State of Ports
Mode Idle Idle Power Down Power Down Program Memory Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT0 Port Data(1) Floating Port Data(1) Floating PORT1 Port Data Port Data Port Data Port Data PORT2 Port Data Address Port Data Port Data PORT3 Port Data Port Data Port Data Port Data
Port 0 can force a 0 level. A "one" will leave port floating.
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Power-off Flag
The Power-off flag allows the user to distinguish between a "cold start" reset and a "warm start" reset. A cold start reset is the one induced by VCC switch-on. A warm start reset occurs while VCC is still applied to the device and could be generated by an exit from Power-down. The Power-off flag (POF) is located in PCON register (Table 63). POF is set by hardware when VCC rises from 0 to its nominal voltage. The POF can be set or cleared by software allowing the user to determine the type of reset. Table 63. PCON Register PCON - Power Control Register (87h)
7 SMOD1 Bit Number 7 6 SMOD0 Bit Mnemonic Description SMOD1 Serial port Mode Bit 1 Set to select double baud rate in mode 1, 2 or 3. Serial port Mode Bit 0 Cleared to select SM0 bit in SCON register. Set to select FE bit in SCON register. Reserved The value read from this bit is indeterminate. Do not set this bit. Power-off Flag Cleared to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. General-purpose Flag Cleared by user for general-purpose usage. Set by user for general-purpose usage. General-purpose Flag Cleared by user for general-purpose usage. Set by user for general-purpose usage. Power-down mode bit Cleared by hardware when reset occurs. Set to enter power-down mode. Idle Mode Bit Cleared by hardware when interrupt or reset occurs. Set to enter idle mode. 5 4 POF 3 GF1 2 GF0 1 PD 0 IDL
6
SMOD0
5
-
4
POF
3
GF1
2
GF0
1
PD
0
IDL
Reset Value = 00X1 0000b Not bit addressable
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Reduced EMI Mode
The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit. The AO bit is located in AUXR register at bit location 0.As soon as AO is set, ALE is no longer output but remains active during MOVX and MOVC instructions and external fetches. During ALE disabling, ALE pin is weakly pulled high. Table 64. AUXR Register AUXR - Auxiliary Register (8Eh)
7 DPU Bit Number 6 Bit Mnemonic Description Disable Weak Pull-up 7 DPU Cleared to activate the permanent weak pull up when latch data is logic 1 Set to disactive the weak pull-up. 6 Reserved The value read from this bit is indeterminate. Do not set this bit. Pulse Length 5 M0 Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock periods (default). Set to stretch MOVX control: the RD and the WR pulse length is 30 clock periods. 4 3 XRS1 Reserved The value read from this bit is indeterminate. Do not set this bit. XRAM Size XRS1 0 2 XRS0 0 1 1 XRS0 0 1 0 1 XRAM size 256 Bytes (default) 512 Bytes 768 Bytes 1024 Bytes 5 M0 4 3 XRS1 2 XRS0 1 EXTRAM 0 AO
EXTRAM Bit Cleared to access internal XRAM using movx @ Ri @ DPTR. 1 EXTRAM Set to access external memory. Programmed by hardware after Power-up regarding Hardware Security Byte (HSB), default setting, XRAM selected. ALE Output Bit Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode is used). (default) Set, ALE is active only during a MOVX or MOVC instruction is used.
0
AO
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Flash EEPROM Memory
The Flash memory increases EPROM and ROM functionality with in-circuit electrical erasure and programming. It contains 16K or 32K Bytes of program memory organized in 128 or 256 pages of 128 Bytes. This memory is both parallel and serial In-system Programmable (ISP). ISP allows devices to alter their own program memory in the actual end product under software control. A default serial loader (bootloader) program allows ISP of the Flash. The programming does not require external dedicated programming voltage. The necessary high programming voltage is generated on-chip using the standard VCC pins of the microcontroller.
Features
* * * * * *
Flash EEPROM internal program memory. Boot vector allows user provided Flash loader code to reside anywhere in the Flash memory space. This configuration provides flexibility to the user. Default loader in Boot ROM allows programming via the serial port without the need of a user-provided loader. Up to 64K Byte external program memory if the internal program memory is disabled (EA = 0). Programming and erase voltage with standard 5V or 3V VCC supply. Read/Programming/Erase: - - Byte-wise read without wait state Byte or page erase and programming (10 ms)
* * * * *
Typical programming time (32K Bytes) in 10 s Parallel programming with 87C51 compatible hardware interface to programmer Programmable security for the code in the Flash 10K write cycles 10 years data retention
Flash Programming and Erasure
The 16K or 32K Bytes Flash is programmed by Bytes or by pages of 128 Bytes. It is not necessary to erase a Byte or a page before programming. The programming of a Byte or a page includes a self erase before programming. There are three methods of programming the Flash memory: * * * First, the on-chip ISP bootloader may be invoked which will use low level routines to program the pages. The interface used for serial downloading of Flash is the UART. Second, the Flash may be programmed or erased in the end-user application by calling low-level routines through a common entry point in the Boot ROM. Third, the Flash may be programmed using the parallel method by using a conventional EPROM programmer. The parallel programming method used by these devices is similar to that used by EPROM 87C51 but it is not identical and the commercially available programmers need to have support for the AT89C51RB2/RC2. The bootloader and the Application Programming Interface (API) routines are located in the BOOT ROM.
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Flash Registers and Memory Map
The AT89C51RB2/RC2 Flash memory uses several registers for its management: * * Hardware registers can only be accessed through the parallel programming modes which are handled by the parallel programmer. Software registers are in a special page of the Flash memory which can be accessed through the API or with the parallel programming modes. This page, called "Extra Flash Memory", is not in the internal Flash program memory addressing space.
Hardware Register
The only hardware register of the AT89C51RB2/RC2 is called Hardware Security Byte (HSB). Table 65. Hardware Security Byte (HSB)
7 X2 Bit Number 6 BLJB Bit Mnemonic 5 4 3 XRAM 2 LB2 1 LB1 0 LB0
Description X2 Mode Programmed to force X2 mode (6 clocks per instruction) after reset. Unprogrammed to force X1 mode, Standard Mode, after reset (Default). Boot Loader Jump Bit
7
X2
6
BLJB
Unprogrammed this bit to start the user's application on next reset at address 0000h. Programmed this bit to start the boot loader at address F800h (Default).
5 4
-
Reserved Reserved XRAM Config Bit (only programmable by programmer tools)
3
XRAM
Programmed to inhibit XRAM after reset. Unprogrammed, this bit to valid XRAM after reset (Default).
2-0
LB2-0
User Memory Lock Bits (only programmable by programmer tools) See Table 66.
Boot Loader Jump Bit (BLJB) One bit of the HSB, the BLJB bit, is used to force the boot address: * * When this bit is set (programmed) value the boot address is 0000h. When this bit is reset (unprogrammed) the boot address is F800h. By default, this bit is reset and the ISP is enabled.
Flash Memory Lock Bits
The three lock bits provide different levels of protection for the on-chip code and data, when programmed as shown in Table 66.
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Table 66. Program Lock Bits
Program Lock Bits Security Level 1
LB0 U
LB1 U
LB2 U
Protection Description No program lock features enabled. MOVC instruction executed from external program memory is disabled from fetching code Bytes from internal memory, EA is sampled and latched on reset, and further parallel programming of the Flash is disabled. ISP and software programming with API are still allowed. Same as 2, also verify through parallel programming interface is disabled. Same as 3, also external execution is disabled. (Default)
2
P
U
U
3 4
X X
P X
U P
Note:
U: unprogrammed or "one" level. P: programmed or "zero" level. X: don't care WARNING: Security level `2' and `3` should only be programmed after Flash and code verification.
These security bits protect the code access through the parallel programming interface. They are set by default to level 4. The code access through the ISP is still possible and is controlled by the "software security bits" which are stored in the extra Flash memory accessed by the ISP firmware. To load a new application with the parallel programmer, a chip erase must first be done. This will set the HSB in its inactive state and will erase the Flash memory. The part reference can always be read using Flash parallel programming modes. Default Values The default value of the HSB provides parts ready to be programmed with ISP: * * * * BLJB: Programmed force ISP operation. X2: Unprogrammed to force X1 mode (Standard Mode). XRAM: Unprogrammed to valid XRAM LB2-0: Security level four to protect the code from a parallel access with maximum security.
Software Registers
Several registers are used, in factory and by parallel programmers, to make copies of hardware registers contents. These values are used by Atmel ISP. These registers are in the "Extra Flash Memory" part of the Flash memory. This block is also called "XAF" or eXtra Array Flash. They are accessed in the following ways: * * * Commands issued by the parallel memory programmer. Commands issued by the ISP software. Calls of API issued by the application software.
Several software registers are described in Table 67.
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Table 67. Default Values
Mnemonic SBV HSB BSB SSB Definition Software Boot Vector Hardware security Byte Boot Status Byte Software Security Byte Copy of the Manufacturer Code Copy of the Device ID #1: Family Code Copy of the Device ID #2: memories size and type Copy of the Device ID #3: name and revision Default value FCh 101x 1011b 0FFh FFh 58h D7h F7h FBh EFh ATMEL C51 X2, Electrically Erasable AT89C51RB2/RC2 32KB AT89C51RB2/RC2 16 KB AT89C51RB2/RC2 32KB, Revision 0 AT89C51RB2/RC2 16 KB, Revision 0 Description
FFh
After programming the part by ISP, the BSB must be cleared (00h) in order to allow the application to boot at 0000h. The content of the Software Security Byte (SSB) is described in Table 67 and Table 69. To assure code protection from a parallel access, the HSB must also be at the required level. Table 68. Software Security Byte
7 Bit Number 7 6 Bit Mnemonic Description Reserved Do not clear this bit. Reserved Do not clear this bit. Reserved Do not clear this bit. Reserved Do not clear this bit. Reserved Do not clear this bit. Reserved Do not clear this bit. User Memory Lock Bits see Table 69 5 4 3 2 1 LB1 0 LB0
6
-
5
-
4
-
3
-
2
-
1-0
LB1-0
The two lock bits provide different levels of protection for the on-chip code and data, when programmed as shown in Table 69. 87
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Table 69. Program Lock Bits of the SSB
Program Lock Bits Security level 1 2 3 LB0 U P X LB1 U U P Protection Description No program lock features enabled. ISP programming of the Flash is disabled. Same as 2, also verify through ISP programming interface is disabled.
Note:
U: unprogrammed or "one" level. P: programmed or "zero" level. X: don't care WARNING: Security level 2 and 3 should only be programmed after Flash and code verification.
Flash Memory Status
AT89C51RB2/RC2 parts are delivered in standard with the ISP boot in the Flash memory. After ISP or parallel programming, the possible contents of the Flash memory are summarized on Figure 34.
Figure 34. Flash Memory Possible Contents 7FFFh T89C51RC2 32KB 3FFFh T89C51RB2 16KB
Virgin
Application
Virgin or Application Dedicated ISP
Application
Virgin or Application
Dedicated ISP After Parallel Programming After Parallel Programming
0000h Default After ISP After ISP
Memory Organization
In the AT89C51RB2/RC2, the lowest 16K or 32K of the 64 KB program memory address space is filled by internal Flash. When the EA pin is high, the processor fetches instructions from internal program Flash. Bus expansion for accessing program memory from 16K or 32K upward automatic since external instruction fetches occur automatically when the program counter exceeds 3FFFh (16K) or 7FFFh (32K). If the EA pin is tied low, all program memory fetches are from external memory.
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Bootloader Architecture
Introduction The bootloader manages a communication according to a specific defined protocol to provide the whole access and service on Flash memory. Furthermore, all accesses and routines can be called from the user application. Figure 35. Diagram Context Description
Access via Specific Protocol
Bootloader
Flash Memory
Access From User Application
Acronyms
ISP: In-system Programming SBV: Software Boot Vector BSB: Boot Status Byte SSB: Software Security Bit HW : Hardware Byte
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Functional Description Figure 36. Bootloader Functional Description Exernal Host with Specific Protocol Communication
User Application
ISP Communication Management
User Call Management (API )
Flash Memory Management
Flash Memory
On the above diagram, the on-chip bootloader processes are: * ISP Communication Management The purpose of this process is to manage the communication and its protocol between the on-chip bootloader and a external device. The on-chip ROM implement a serial protocol (see section Bootloader Protocol). This process translate serial communication frame (UART) into Flash memory acess (read, write, erase ...). * User Call Management
Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of Flash pages. All calls are made through a common interface (API calls), included in the ROM bootloader. The programming functions are selected by setting up the microcontroller's registers before making a call to a common entry point (0xFFF0). Results are returned in the registers. The purpose on this process is to translate the registers values into internal Flash Memory Management.
*
Flash Memory Management
This process manages low level access to Flash memory (performs read and write access).
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Bootloader Functionality Introduction The bootloader can be activated by two means: Hardware conditions or regular boot process. The Hardware conditions (EA = 1, PSEN = 0) during the Reset# falling edge force the on-chip bootloader execution. This allows an application to be built that will normally execute the end user's code but can be manually forced into default ISP operation. As PSEN is an output port in normal operating mode (running user application or boorloader code) after reset, it is recommended to release PSEN after falling edge of reset signal. The hardware conditions are sampled at reset signal falling edge, thus they can be released at any time when reset input is low. The on-chip bootloader boot process is shown in Figure 37.
Purpose Hardware Conditions The Hardware Conditions force the bootloader execution whatever BLJB, BSB and SBV values. The Boot Loader Jump Bit forces the application execution. BLJB = 0 => Boot loader execution. BLJB = 1 => Application execution. BLJB The BLJB is a fuse bit in the Hardware Byte. That can be modified by hardware (programmer) or by software (API). Note: The BLJB test is perform by hardware to prevent any program execution. The Software Boot Vector contains the high address of custumer bootloader stored in the application. SBV = FCh (default value) if no custumer bootloader in user Flash. SBV Note: The costumer bootloader is called by JMP [SBV]00h instruction.
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Boot Process Figure 37. Bootloader process
RESET
If BLJB = 0 then ENBOOT bit (AUXR1) is set else ENBOOT bit (AUXR1) is cleared
Yes (PSEN = 0, EA = 1, and ALE = 1 or not connected)
Hardware
Hardware Condition?
FCON = 00h
FCON = F0h
BLJB = 1
ENBOOT = 0
BLJB!= 0 ?
BLJB = 0 ENBOOT = 1
F800h
Software
FCON = 00h ?
yes = hardware boot conditions
BSB = 00h ?
PC = 0000h USER APPLICATION
SBV = FCh ?
USER BOOT LOADER
Atmel BOOT LOADER
PC= [SBV]00h
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ISP Protocol Description
Physical Layer The UART used to transmit information has the following configuration: * * * * * Character: 8-bit data Parity: none Stop: 1 bit Flow control: none Baud rate: autobaud is performed by the bootloader to compute the baud rate choosen by the host.
Frame Description
The Serial Protocol is based on the Intel Hex-type records. Intel Hex records consist of ASCII characters used to represent hexadecimal values and are summarized below. Table 70. Intel Hex Type Frame
Record Mark `:' 1 byte Reclen 1 byte Load Offset 2 bytes Record Type 1 bytes Data or Info n byte Checksum 1 byte
* *
Record Mark: - - Record Mark is the start of frame. This field must contain ':'. Reclen specifies the number of Bytes of information or data which follows the Record Type field of the record. Load Offset specifies the 16-bit starting load offset of the data Bytes, therefore this field is used only for Data Program Record (see Section "ISP Commands Summary"). Record Type specifies the command type. This field is used to interpret the remaining information within the frame. The encoding for all the current record types is described in Section "ISP Commands Summary". Data/Info is a variable length field. It consists of zero or more Bytes encoded as pairs of hexadecimal digits. The meaning of data depends on the Record Type. The two's complement of the 8-bit Bytes that result from converting each pair of ASCII hexadecimal digits to one Byte of binary, and including the Reclen field to and including the last Byte of the Data/Info field. Therefore, the sum of all the ASCII pairs in a record after converting to binary, from the Reclen field to and including the Checksum field, is zero. Reclen:
*
Load Offset: - -
*
Record Type: -
*
Data/Info: -
*
Checksum: -
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Functional Description
Software Security Bits (SSB) The SSB protects any Flash access from ISP command. The command "Program Software Security bit" can only write a higher priority level. There are three levels of security: * level 0: NO_SECURITY (FFh) This is the default level. From level 0, one can write level 1 or level 2. * level 1: WRITE_SECURITY (FEh )
For this level it is impossible to write in the Flash memory, BSB and SBV. The Bootloader returns 'P' on write access. From level 1, one can write only level 2. * level 2: RD_WR_SECURITY (FCh
The level 2 forbids all read and write accesses to/from the Flash/EEPROM memory. The Bootloader returns 'L' on read or write access. Only a full chip erase in parallel mode (using a programmer) or ISP command can reset the software security bits. From level 2, one cannot read and write anything. Table 71. Software Security Byte Behavior
Level 0 Flash/EEPROM Fuse Bit BSB & SBV SSB Manufacturer Info Bootloader Info Erase Block Full-chip Erase Blank Check Any access allowed Any access allowed Any access allowed Any access allowed Read only access allowed Read only access allowed Allowed Allowed Allowed Level 1 Read only access allowed Read only access allowed Read only access allowed Write level 2 allowed Read only access allowed Read only access allowed Not allowed Allowed Allowed Level 2 Any access not allowed Any access not allowed Any access not allowed Read only access allowed Read only access allowed Read only access allowed Not allowed Allowed Allowed
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Full Chip Erase The ISP command "Full Chip Erase" erases all User Flash memory (fills with FFh) and sets some Bytes used by the bootloader at their default values: * * * BSB = FFh SBV = FCh SSB = FFh and finally erase the Software Security Bits
The Full Chip Erase does not affect the bootloader. Checksum Error When a checksum error is detected send `X' followed with CR&LF.
Flow Description
Overview An initialization step must be performed after each Reset. After microcontroller reset, the bootloader waits for an autobaud sequence ( see section `autobaud performance'). When the communication is initialized the protocol depends on the record type requested by the host. FLIP, a software utility to implement ISP programming with a PC, is available from the Atmel the web site. Communication Initialization The host initializes the communication by sending a 'U' character to help the bootloader to compute the baudrate (autobaud). Figure 38. Initialization Host Init Communication "U" Bootloader
Performs Autobaud Sends Back `U' Character
If (not received "U") Else Communication Opened
"U"
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Autobaud Performances
The ISP feature allows a wide range of baud rates in the user application. It is also adaptable to a wide range of oscillator frequencies. This is accomplished by measuring the bit-time of a single bit in a received character. This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. The ISP featur e requir es that an initial char acter ( an uppercase U) be sent to the AT89C51RB2/RC2 to establish the baud rate. Table 72 shows the autobaud capability.
Table 72. Autobaud Performances
Frequency (MHz) Baudrate (bit/s) 2400 4800 9600 19200 38400 57600 115200 1.8432 OK OK OK OK 2 OK 2.4576 OK OK OK OK OK 3 OK OK OK OK 3.6864 OK OK OK OK OK OK 4 OK OK OK 5 OK OK OK OK 6 OK OK OK OK OK 7.3728 OK OK OK OK OK OK OK 8 OK OK OK OK
Frequency (MHz) Baudrate (bit/s) 2400 4800 9600 19200 38400 57600 115200 10 OK OK OK OK 11.0592 OK OK OK OK OK OK OK 12 OK OK OK OK OK 14.318 OK OK OK OK OK OK OK 14.746 OK OK OK OK OK OK OK 16 OK OK OK OK OK OK 20 OK OK OK OK OK OK 24 OK OK OK OK OK OK 26.6 OK OK OK OK OK OK -
Command Data Stream Protocol
All commands are sent using the same flow. Each frame sent by the host is echoed by the bootloader.
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Figure 39. Command Flow Host Sends first character of the Frame ":" ":" Bootloader If (not received ":") Else Sends echo and start reception
Sends frame (made of 2 ASCII characters per Byte) Echo analysis
Gets frame, and sends back ec for each received Byte
Write/Program Commands
This flow is common to the following frames: * * * * Flash/EEPROM Programming Data Frame EOF or Atmel Frame (only Programming Atmel Frame) Config Byte Programming Data Frame Baud Rate Frame
Description Figure 40. Write/Program Flow Host
Send Write Command
Bootloader Write Command
Wait Write Command
OR
Wait Checksum Error
Checksum error
'X' & CR & LF
Send Checksum error
COMMAND ABORTED
NO_SECURITY
OR
Wait Security Error
'P' & CR & LF
Send Security error
COMMAND ABORTED
Wait Programming
Wait COMMAND_OK
'.' & CR & LF
Send COMMAND_OK
COMMAND FINISHED
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Example Programming Data (write 55h at address 0010h in the Flash)
HOST BOOTLOADER : 01 0010 00 55 9A : 01 0010 00 55 9A . CR LF
Programming Atmel function (write SSB to level 2)
HOST BOOTLOADER : 02 0000 03 05 01 F5 : 02 0000 03 05 01 F5. CR LF
Writing Frame (write BSB to 55h)
HOST BOOTLOADER : 03 0000 03 06 00 55 9F : 03 0000 03 06 00 55 9F . CR LF
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Blank Check Command Description Figure 41. Blank Check Flow Host
Send Blank Check Command
Bootloader Blank Check Command
Wait Blank Check Command
OR
Wait Checksum Error
Checksum error
'X' & CR & LF
Send Checksum error
COMMAND ABORTED
Flash blank
OR
Wait COMMAND_OK
'.' & CR & LF
Send COMMAND_OK
COMMAND FINISHED
Wait Address not erased
address & CR & LF
Send first Address not erased
COMMAND FINISHED
Example Blank Check ok
HOST BOOTLOADER : 05 0000 04 0000 7FFF 01 78 : 05 0000 04 0000 7FFF 01 78 . CR LF
Blank Check ko at address xxxx
HOST BOOTLOADER : 05 0000 04 0000 7FFF 01 78 : 05 0000 04 0000 7FFF 01 78 xxxx CR LF
Blank Check with checksum error
HOST BOOTLOADER : 05 0000 04 0000 7FFF 01 70 : 05 0000 04 0000 7FFF 01 70 X CR LF CR LF
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Display Data Description Figure 42. Display Flow Host
Send Display Command
Bootloader Display Command
Wait Display Command
OR
Wait Checksum Error
Checksum error
'X' & CR & LF
Send Checksum Error
COMMAND ABORTED
RD_WR_SECURITY
OR
Wait Security Error
'L' & CR & LF
Send Security Error
COMMAND ABORTED
Read Data
All data read
Complete Frame
Wait Display Data
"Address = " "Reading value" CR & LF
Send Display Data
All data read
All data read
COMMAND FINISHED
COMMAND FINISHED
Note:
The maximum size of block is 400h. To read more than 400h Bytes, the Host must send a new command.
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Example Display data from address 0000h to 0020h
HOST BOOTLOADER BOOTLOADER BOOTLOADER BOOTLOADER : 05 0000 04 0000 0020 00 D7 : 05 0000 04 0000 0020 00 D7 0000=-----data------ CR LF 0010=-----data------ CR LF 0020=data CR LF (16 data) (16 data) ( 1 data)
Read Function
This flow is similar for the following frames: * * Reading Frame EOF Frame/Atmel Frame (only reading Atmel Frame)
Description Figure 43. Read Flow Host
Send Read Command
Bootloader Read Command
Wait Read Command
OR
Wait Checksum Error
Checksum error
'X' & CR & LF
Send Checksum error
COMMAND ABORTED
RD_WR_SECURITY
OR
Wait Security Error
'L' & CR & LF
Send Security error
COMMAND ABORTED
Read Value
Wait Value of Data
'value' & '.' & CR & LF
Send Data Read
COMMAND FINISHED
Example Read function (read SBV)
HOST BOOTLOADER : 02 0000 05 07 02 F0 : 02 0000 05 07 02 F0 Value . CR LF
Atmel Read function (read Bootloader version)
HOST BOOTLOADER : 02 0000 01 02 00 FB : 02 0000 01 02 00 FB Value . CR LF
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ISP Commands Summary
Table 73. ISP Commands Summary
Command Command Name Data[0] Data[1] Command Effect Program Nb Data Byte. 00h Program Data Bootloader will accept up to 128 (80h) data Bytes. The data Bytes should be 128 Byte page Flash boundary. 00h 20h 01h 40h 80h C0h 00h 03h 01h 04h 03h Write Function 05h 01h 00h 06h 01h 07h 02h 0Ah 04h 08h Program SBV (value to write in data[2]) Full Chip Erase Program Osc fuse (value to write in data[2]) Program BLJB fuse (value to write in data[2]) Program X2 fuse (value to write in data[2]) Display Data Note: The maximum number of data that can be read with a single Data[4] = 00h -> Display data command frame (difference between start and end address) is 1kbyte. Data[4] = 01h -> Blank check Blank Check Data [2:3] = end address 00h 01h 00h 02h 03h 00h 01h 05h Read Function 07h 02h 06h 0Bh 0Eh 01h 0Fh 00h Read Device Boot ID2 Read Bootloader Version 00h 00h Read SBV Read Extra Byte Read Hardware Byte Read Device Boot ID1 Device ID #2 Device ID #3 Read SSB Read BSB Manufacturer ID Device ID #1 Data[0:1] = start address Program SSB level 2 Program BSB (value to write in data[2]) 00h 00h Ljmp Address (data[2:3]= Address) Erase SBV & BSB Program SSB level 1 Erase block0 (0000h-1FFFh) Erase block1 (2000h-3FFFh) Erase block2 (4000h-7FFFh) Erase block3 (8000h- BFFFh) Erase block4 (C000h- FFFFh) Hardware Reset
04h
Display Function
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API Call Description
Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of Flash pages. All calls are made through a common interface, PGM_MTP. The programming functions are selected by setting up the microcontroller's registers before making a call to PGM_MTP at FFF0h. Results are returned in the registers. When several Bytes have to be programmed, it is highly recommended to use the Atmel API "PROGRAM DATA PAGE" call. Indeed, this API call writes up to 128 Bytes in a single command. All routines for software access are provided in the C Flash driver available at Atmel's web site. The API calls description and arguments are shown in Table 74. Table 74. API Call Summary
Command READ MANUF ID READ DEVICE ID1 READ DEVICE ID2 READ DEVICE ID3 R1 00h 00h 00h 00h A XXh XXh XXh XXh DPTR0 0000h 0001h 0002h 0003h DPH = 00h ERASE BLOCK 01h XXh DPH=20h DPH=40h PROGRAM DATA BYTE ERASE BOOT VECTOR Byte value to program XXh Address of Byte to program XXh DPH = 00h DPL = 00h DPH = 00h DPL = 01h PROGRAM SSB 05h XXh DPH = 00h DPL = 10h DPH = 00h DPL = 11h PROGRAM BSB PROGRAM SBV READ SSB READ HSB READ BSB READ SBV 06h 06h 07h 07h 07h 07h New BSB value New SBV value XXh XXh XXh XXh 0000h 0001h 0000h 0004h 0001h 0002h XXh XXh XXh XXh XXh XXh none none ACC=SSB ACC=HSB ACC=BSB ACC=SBV 00h ACC= SSB value Set SSB level 0 XXh ACC = 0 : DONE 00h ACC=DPH DPTR1 XXh XXh XXh XXh Returned Value ACC=Manufacturer ID ACC= Device ID 1 ACC=Device ID 2 ACC=Device ID 3 Command Effect Read Manufacturer identifier Read Device identifier 1 Read Device identifier 2 Read Device identifier 3 Erase block 0 (from 0x0000 to 0x1FFF) Erase block 1 (from 0x2000 to 0x3FFF) Erase block 2 (from 0x4000 to 0x7FFF) (AT89C51RC2 device only) Program one Data Byte in user Flash Erase Software boot vector and boot status Byte. (SBV=FCh and BSB=FFh) Set SSB level 1
02h
04h
ACC=FCh
Set SSB level 2
Set SSB level 1 Program boot status Byte Program software boot vector Read Software Security Byte Read Hardware Byte Read Boot Status Byte Read Software Boot Vector
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Table 74. API Call Summary (Continued)
Command READ MANUF ID READ DEVICE ID1 READ DEVICE ID2 READ DEVICE ID3 R1 00h 00h 00h 00h A XXh XXh XXh XXh DPTR0 0000h 0001h 0002h 0003h DPH = 00h ERASE BLOCK 01h XXh DPH=20h DPH=40h Address of the first Byte to program in the Flash memory 0008h 00h ACC=DPH DPTR1 XXh XXh XXh XXh Returned Value ACC=Manufacturer ID ACC= Device ID 1 ACC=Device ID 2 ACC=Device ID 3 Command Effect Read Manufacturer identifier Read Device identifier 1 Read Device identifier 2 Read Device identifier 3 Erase block 0 (from 0x0000 to 0x1FFF) Erase block 1 (from 0x2000 to 0x3FFF) Erase block 2 (from 0x4000 to 0x7FFF) (AT89C51RC2 device only) Address in XRAM of the first data to program Program up to 128 Bytes in user Flash. ACC = 0 : DONE Remark: number of Bytes to program is limited such as the Flash write remains in a single 128 Bytes page. Hence, when ACC is 128, valid values of DPL are 00h, or 80h. Program X2 fuse bit with ACC
PROGRAM DATA PAGE
09h
Number of Byte to program Fuse value 00h or 01h Fuse value 00h or 01h XXh XXh XXh
PROGRAM X2 FUSE PROGRAM BLJB FUSE READ BOOT ID1 READ BOOT ID2 READ BOOT VERSION
0Ah
XXh
none
0Ah 0Eh 0Eh 0Fh
0004h DPL = 00h DPL = 01h XXXXh
XXh XXh XXh XXh
none ACC=ID1 ACC=ID2 ACC=Boot_Version
Program BLJB fuse bit with ACC Read boot ID1 Read boot ID2 Read bootloader version
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Electrical Characteristics Absolute Maximum Ratings
Note: C = commercial......................................................0C to 70C I = industrial ........................................................-40C to 85C Storage Temperature .................................... -65C to + 150C Voltage on VCC to VSS (standard voltage) .........-0.5V to + 6.5V Voltage on VCC to VSS (low voltage)..................-0.5V to + 4.5V Voltage on Any Pin to VSS ..........................-0.5V to VCC + 0.5V Power Dissipation .............................................................. 1 W Stresses at or above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Power dissipation value is based on the maximum allowable die temperature and the thermal resistance of the package.
DC Parameters for Standard Voltage
TA = 0C to +70C; VSS = 0V; VCC = 2.7V to 5.5V; F = 0 to 48 MHz TA = -40C to +85C; VSS = 0V; VCC =2.7V to 5.5V; F = 0 to 48 MHz
Symbol VIL VIH VIH1(9) Parameter Input Low Voltage Input High Voltage except RST, XTAL1 Input High Voltage RST, XTAL1 Min -0.5 0.2 VCC + 0.9 0.7 VCC Typ Max 0.2 VCC - 0.1 VCC + 0.5 VCC + 0.5 Unit V V V VCC = 4.5V to 5.5V 0.3 0.45 VOL Output Low Voltage, ports 1, 2, 3, 4 (6) 1.0 V V V IOL = 100 A(4) IOL = 1.6 mA(4) IOL = 3.5 mA(4) VCC = 2.7V to 5.5V 0.45 V IOL = 0.8 mA(4) VCC = 4.5V to 5.5V 0.3 0.45 VOL1 Output Low Voltage, port 0, ALE, PSEN (6) 1.0 V V V IOL = 200 A(4) IOL = 3.2 mA(4) IOL = 7.0 mA(4) VCC = 2.7V to 5.5V 0.45 V IOL = 1.6 mA(4) VCC = 5V 10% VCC - 0.3 VCC - 0.7 VOH Output High Voltage, ports 1, 2, 3, 4 VCC - 1.5 V V V IOH = -10 A IOH = -30 A IOH = -60 A Test Conditions
VCC = 2.7V to 5.5V 0.9 VCC V IOH = -10 A
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TA = 0C to +70C; VSS = 0V; VCC = 2.7V to 5.5V; F = 0 to 48 MHz TA = -40C to +85C; VSS = 0V; VCC =2.7V to 5.5V; F = 0 to 48 MHz (Continued)
Symbol Parameter Min Typ Max Unit Test Conditions VCC = 5V 10% VCC - 0.3 VCC - 0.7 VOH1 Output High Voltage, port 0, ALE, PSEN VCC - 1.5 V V V IOH = -200 A IOH = -3.2 mA IOH = -7.0 mA
VCC = 2.7V to 5.5V 0.9 VCC RRST IIL ILI ITL CIO IPD ICCOP ICCIDLE ICCProg RST Pulldown Resistor Logical 0 Input Current ports 1, 2, 3, 4 and 5 Input Leakage Current for P0 only Logical 1 to 0 Transition Current, ports 1, 2, 3, 4 Capacitance of I/O Buffer Power Down Current Power Supply Current on normal mode Power Supply Current on idle mode 0.4 x Frequency (MHz) + 20 100 50 200
(5)
V 250 -50 10 -650 10 150 0.4 x Frequency (MHz) + 5 0.3 x Frequency (MHz) + 5 k A A A pF A mA mA
IOH = -10 A
VIN = 0.45V 0.45V < VIN < VCC VIN = 2.0V Fc = 3 MHz TA = 25C 4.5V < VCC < 5.5V(3) VCC = 5.5V(1) VCC = 5.5V(1) VCC = 5.5V(8)
Power Supply Current during flash Write / Erase
mA
Notes:
1. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 47.), VIL = VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used (see Figure 44). 2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5V, VIH = VCC 0.5V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 45). 3. Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Figure 46). 4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary. 5. Typical are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V. 6. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1, 2 and 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 7. For other values, please contact your sales office. 8. Icc Flash Write operation current while an on-chip flash page write is on going. 9. Flash Retention is guaranteed with the same formula for VCC Min down to 0.
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DC Parameters for Low Voltage
TA = 0C to +70C; VSS = 0V; VCC = 2.7V to 3.6V; F = 0to 48 MHz TA = -40C to +85C; VSS = 0V; VCC = 2.7V to 3.6V; F = 0 to 48 MHz
Symbol VIL VIH VIH1 VOL VOL1 VOH VOH1 IIL ILI ITL RRST CIO IPD ICCOP ICCIDLE Parameter Input Low Voltage Input High Voltage except RST, XTAL1 Input High Voltage, RST, XTAL1 Output Low Voltage, ports 1, 2, 3, 4(6) Output Low Voltage, port 0, ALE, PSEN (6) Output High Voltage, ports 1, 2, 3, 4 Output High Voltage, port 0, ALE, PSEN Logical 0 Input Current ports 1, 2, 3, 4 Input Leakage Current for P0 only Logical 1 to 0 Transition Current, ports 1, 2, 3, RST Pulldown Resistor Capacitance of I/O Buffer 10 (5) 50 200
(5)
Min -0.5 0.2 VCC + 0.9 0.7 VCC
Typ
Max 0.2 VCC - 0.1 VCC + 0.5 VCC + 0.5 0.45 0.45
Unit V V V V V V V
Test Conditions
IOL = 0.8 mA(4) IOL = 1.6 mA(4) IOH = -10 A IOH = -40 A VIN = 0.45 V 0.45V < VIN < VCC VIN = 2.0V
0.9 VCC 0.9 VCC -50 10 -650 250 10
A A A k pF A mA mA
Fc = 3 MHz TA = 25C VCC = 2.7V to 3.6V(3) VCC = 3.6 V(1) VCC = 3.6 V(2)
Power Down Current Power Supply Current on normal mode Power Supply Current on idle mode
50 0.4 x Frequency (MHz) + 5 0.3 x Frequency (MHz) + 5
ICCProg
Power Supply Current during flash Write / Erase
0.4 x Frequency (MHz) + 20
mA
VCC = 5.5V(8)
Notes:
1. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 47.), VIL = VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used (see Figure 44). 2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5V, VIH = VCC 0.5V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 45). 3. Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Figure 46). 4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary. 5. Typical are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V. 6. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1, 2 and 3: 15 mA Maximum total IOL for all output pins: 71 mA
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If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 7. For other values, please contact your sales office. 8. Icc Flash Write operation current while an on-chip flash page write is on going.
Figure 44. ICC Test Condition, Active Mode
VCC ICC VCC VCC RST (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS All other pins are disconnected. P0 EA VCC
Figure 45. ICC Test Condition, Idle Mode
VCC ICC VCC P0 RST (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS All other pins are disconnected. EA VCC
Figure 46. ICC Test Condition, Power-down Mode
VCC ICC VCC P0 RST (NC) XTAL2 XTAL1 VSS All other pins are disconnected. EA VCC
Figure 47. Clock Signal Waveform for ICC Tests in Active and Idle Modes
VCC-0.5V 0.45V TCLCH TCHCL TCLCH = TCHCL = 5ns. 0.7VCC 0.2VCC-0.1
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AC Parameters
Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a "T" (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. Example:TAVLL = Time for Address Valid to ALE Low. TLLPL = Time for ALE Low to PSEN Low. (Load Capacitance for port 0, ALE and PSEN = 100 pF; Load Capacitance for all other outputs = 80 pF.) Table 75 Table 78, and Table 80 give the description of each AC symbols. Table 77, Table 79 and Table 81 give the AC parameterfor each range. Table 76, Table 77 and Table 82 gives the frequency derating formula of the AC parameter for each speed range description. To calculate each AC symbols, take the x value in the correponding column (-M or -L) and use this value in the formula. Example: TLLIU for -M and 20 MHz, Standard clock. x = 35 ns T 50 ns TCCIV = 4T - x = 165 ns External Program Memory Characteristics Table 75. Symbol Description
Symbol T TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ Parameter Oscillator clock period ALE pulse width Address Valid to ALE Address Hold after ALE ALE to Valid Instruction In ALE to PSEN PSEN Pulse Width PSEN to Valid Instruction In Input Instruction Hold after PSEN Input Instruction Float after PSEN Address to Valid Instruction In PSEN Low to Address Float
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Table 76. AC Parameters for a Fix Clock
Symbol Min T TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ 0 10 80 10 5 50 30 0 10 80 10 25 35 5 5 n 65 5 50 30 -M Max Min 25 35 5 5 65 -L Max ns ns ns ns ns ns ns ns ns ns ns ns Units
Table 77. AC Parameters for a Variable Clock
Symbol TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ Type Min Min Min Max Min Min Max Min Max Max Max Standard Clock 2T-x T-x T-x 4T-x T-x 3T-x 3T-x x T-x 5T-x x X2 Clock T-x 0.5 T - x 0.5 T - x 2T-x 0.5 T - x 1.5 T - x 1.5 T - x x 0.5 T - x 2.5 T - x x X Parameter for M Range 15 20 20 35 15 25 45 0 15 45 10 X Parameter for -L Range 15 20 20 35 15 25 45 0 15 45 10 Units ns ns ns ns ns ns ns ns ns ns ns
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External Program Memory Read Cycle
12 TCLCL TLHLL ALE TLLIV TLLPL TPLPH PSEN TLLAX TAVLL PORT 0 INSTR IN A0-A7 TAVIV PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 ADDRESS A8-A15 TPLIV TPLAZ TPXIX INSTR IN A0-A7 INSTR IN TPXAV TPXIZ
External Data Memory Characteristics
Table 78. Symbol Description
Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH Parameter RD Pulse Width WR Pulse Width RD to Valid Data In Data Hold After RD Data Float After RD ALE to Valid Data In Address to Valid Data In ALE to WR or RD Address to WR or RD Data Valid to WR Transition Data set-up to WR High Data Hold After WR RD Low to Address Float RD or WR High to ALE high
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Table 79. AC Parameters for a Fix Clock
-M Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH 45 70 5 155 10 0 5 45 0 25 155 160 105 45 70 5 155 10 0 5 45 Min 125 125 95 0 25 155 160 105 Max Min 125 125 95 -L Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH TWHLH
Type Min Min Max Min Max Max Max Min Max Min Min Min Min Max Min Max
Standard Clock 6T-x 6T-x 5T-x x 2T-x 8T-x 9T-x 3T-x 3T+x 4T-x T-x 7T-x T-x x T-x T+x
X2 Clock 3T-x 3T-x 2.5 T - x x T-x 4T -x 4.5 T - x 1.5 T - x 1.5 T + x 2T-x 0.5 T - x 3.5 T - x 0.5 T - x x 0.5 T - x 0.5 T + x
X Parameter for M Range 25 25 30 0 25 45 65 30 30 30 20 20 15 0 20 20
X Parameter for L Range 25 25 30 0 25 45 65 30 30 30 20 20 15 0 20 20
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
External Data Memory Write Cycle
ALE TWHLH
PSEN
TLLWL
TWLWH
WR TLLAX PORT 0 A0-A7 TAVWL PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 OR SFR P2 TQVWX TQVWH DATA OUT TWHQX
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External Data Memory Read Cycle
ALE TLLDV TWHLH
PSEN
TLLWL
TRLRH
RD TAVDV TLLAX PORT 0 A0-A7 TAVWL PORT 2 ADDRESS OR SFR-P2 TRLAZ ADDRESS A8-A15 OR SFR P2 TRHDX DATA IN
TRHDZ
Serial Port Timing - Shift Register Mode
Table 80. Symbol Description
Symbol TXLXL TQVHX TXHQX TXHDX TXHDV Parameter Serial port clock cycle time Output data set-up to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid
Table 81. AC Parameters for a Fix Clock
-M Symbol TXLXL TQVHX TXHQX TXHDX TXHDV Min 300 200 30 0 117 Max Min 300 200 30 0 117 -L Max Units ns ns ns ns ns
Table 82. AC Parameters for a Variable Clock
Symbol TXLXL TQVHX TXHQX TXHDX TXHDV Type Min Min Min Min Max Standard Clock 12 T 10 T - x 2T-x x 10 T - x X2 Clock 6T 5T-x T-x x 5 T- x 50 20 0 133 50 20 0 133 X Parameter for M Range X Parameter for -L Range Units ns ns ns ns ns
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Shift Register Timing Waveforms
INSTRUCTION ALE TXLXL CLOCK TQVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI 0 TXHDV
VALID VALID
0
1
2
3
4
5
6
7
8
TXHQX 1 2 TXHDX
VALID VALID VALID VALID VALID
3
4
5
6
7 SET TI
VALID
SET RI
External Clock Drive Waveforms
VCC-0.5V 0.45V
0.7VCC 0.2VCC-0.1 TCHCL TCLCX TCLCL TCHCX TCLCH
AC Testing Input/Output Waveforms
INPUT/OUTPUT
VCC -0.5V 0.45 V
0.2 VCC + 0.9 0.2 VCC - 0.1
AC inputs during testing are driven at VCC - 0.5 for a logic "1" and 0.45V for a logic "0". Timing measurement are made at VIH min for a logic "1" and VIL max for a logic "0". Float Waveforms
FLOAT VOH - 0.1 V VOL + 0.1 V VLOAD VLOAD + 0.1 V VLOAD - 0.1 V
For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH 20mA. Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.
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Figure 48. Internal Clock Signals INTERNAL
CLOCK XTAL2 ALE EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED FLOAT P2 (EXT) READ CYCLE RD PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) PCL OUT DATA SAMPLED FLOAT INDICATES ADDRESS TRANSITIONS PCL OUT DATA SAMPLED FLOAT PCL OUT THESE SIGNALS ARE NOT ACTIVATED DURING THE EXECUTION OF A MOVX INSTRUCTION STATE4 P1 P2 STATE5 P1 P2 STATE6 P1 P2 STATE1 P1 P2 STATE2 P1 P2 STATE3 P1 P2 STATE4 P1 P2 STATE5 P1 P2
P0
DPL OR Rt OUT
DATA SAMPLED FLOAT
P2 WRITE CYCLE
INDICATES DPH OR P2 SFR TO PCH TRANSITION
WR P0
DPL OR Rt OUT DATA OUT P2
PCL OUT (EVEN IF PROGRAM MEMORY IS INTERNAL)
PCL OUT (IF PROGRAM MEMORY IS EXTERNAL)
INDICATES DPH OR P2 SFR TO PCH TRANSITION
PORT OPERATION MOV PORT SRC MOV DEST P0 MOV DEST PORT (P1. P2. P3) (INCLUDES INTO. INT1. TO T1) SERIAL PORT SHIFT CLOCK TXD (MODE 0) P1, P2, P3 PINS SAMPLED P1, P2, P3 PINS SAMPLED OLD DATA NEW DATA P0 PINS SAMPLED P0 PINS SAMPLED
RXD SAMPLED
RXD SAMPLED
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (TA = 25C fully loaded) RD and WR propagation delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications.
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Ordering Information
Table 83. Possible Order Entries
Part Number AT89C51RB2-3CSIM AT89C51RB2-SLSCM AT89C51RB2-SLSIM AT89C51RB2-SLSIL AT89C51RB2-RLTCM AT89C51RB2-RLTIM AT89C51RB2-RLTIL AT89C51RC2-3CSCM AT89C51RC2-3CSIM AT89C51RC2-SLSCM AT89C51RC2-SLSIM AT89C51RC2-SLSIL AT89C51RC2-RLTCM AT89C51RC2-RLTIM AT89C51RC2-RLTIL Memory Size 16 KBytes 16 KBytes 16 KBytes 16 KBytes 16 KBytes 16 KBytes 16 KBytes 32 KBytes 32 KBytes 32 KBytes 32 KBytes 32 KBytes 32 KBytes 32 KBytes 32 KBytes Supply Voltage 5V 5V 5V 3V 5V 5V 3V 5V 5V 5V 5V 3V 5V 5V 3V Temperature Range Industrial Commercial Industrial Industrial Commercial Industrial Industrial Commercial Industrial Commercial Industrial Industrial Commercial Industrial Industrial Package PDIL40 PLCC44 PLCC44 PLCC44 VQFP44 VQFP44 VQFP44 PDIL40 PDIL40 PLCC44 PLCC44 PLCC44 VQFP44 VQFP44 VQFP44 Packing Stick Stick Stick Stick Tray Tray Tray Stick Stick Stick Stick Stick Tray Tray Tray
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Package Information
PDIL40
118
AT89C51RB2/RC2
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AT89C51RB2/RC2
VQFP44
PLC44
119
4180B-8051-04/03
120
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AT89C51RB2/RC2
Datasheet Change Log
Changes from 4180A-08/02 to 4180B04/03
1. Changed the endurance of Flash to 100, 000 Write/Erase cycles. 2. Added note on Flash retention formula for VIH1, in Section "DC Parameters for Standard Voltage", page 105.
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Table of Contents
Table of Contents
Features ................................................................................................. 1 Description ............................................................................................ 1 Block Diagram ....................................................................................... 2 SFR Mapping ......................................................................................... 3 Pin Configurations ................................................................................ 8 Oscillator ............................................................................................. 12
Registers ............................................................................................................ 12 Functional Block Diagram .................................................................................. 13
Enhanced Features ............................................................................. 14
X2 Feature.......................................................................................................... 14
Dual Data Pointer Register (DPTR) ................................................... 18 Expanded RAM (XRAM) ...................................................................... 21
Registers ............................................................................................................ 23
Timer 2 ................................................................................................. 24
Auto-reload Mode ............................................................................................... 24 Programmable Clock-out Mode.......................................................................... 25 Registers ............................................................................................................ 27
Programmable Counter Array (PCA) ................................................. 29
Registers ............................................................................................................ PCA Capture Mode ............................................................................................ 16-bit Software Timer/ Compare Mode .............................................................. High-speed Output Mode ................................................................................... Pulse Width Modulator Mode ............................................................................. PCA Watchdog Timer......................................................................................... 31 37 38 39 40 40
Serial I/O Port ...................................................................................... 42
Framing Error Detection ..................................................................................... Automatic Address Recognition ......................................................................... Registers ............................................................................................................ Baud Rate Selection for UART for Mode 1 and 3 .............................................. 42 43 45 45
i
UART Registers.................................................................................................. 48
Interrupt System ................................................................................. 53
Registers............................................................................................................. 54 Interrupt Sources and Vector Addresses............................................................ 61
Keyboard Interface ............................................................................. 62
Registers............................................................................................................. 63
Serial Port Interface (SPI) ................................................................... 66
Features.............................................................................................................. 66 Signal Description............................................................................................... 66 Functional Description ........................................................................................ 68
Hardware Watchdog Timer ................................................................ 75
Using the WDT ................................................................................................... 75 WDT During Power-down and Idle ..................................................................... 76
ONCETM Mode (ON Chip Emulation) .................................................. 77 Power Management ............................................................................ 78
Reset .................................................................................................................. Reset Recommendation to Prevent Flash Corruption ........................................ Idle Mode ............................................................................................................ Power-down Mode.............................................................................................. 78 80 80 80
Power-off Flag ..................................................................................... 82 Reduced EMI Mode ............................................................................. 83 Flash EEPROM Memory ..................................................................... 84
Features.............................................................................................................. 84 Flash Programming and Erasure........................................................................ 84 Flash Registers and Memory Map...................................................................... 85 Flash Memory Status.......................................................................................... 88 Memory Organization ......................................................................................... 88 Bootloader Architecture ...................................................................................... 89 ISP Protocol Description..................................................................................... 93 Functional Description ........................................................................................ 94 Flow Description ................................................................................................. 95 API Call Description.......................................................................................... 103
Electrical Characteristics ................................................................. 105
Absolute Maximum Ratings ..............................................................................105 DC Parameters for Standard Voltage ............................................................... 105 DC Parameters for Low Voltage ....................................................................... 107
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4180B-8051-04/03
AC Parameters ................................................................................................. 109
Ordering Information ........................................................................ 117 Package Information ........................................................................ 118
PDIL40.............................................................................................................. 118 VQFP44 ............................................................................................................ 119 PLC44............................................................................................................... 119
Datasheet Change Log ..................................................................... 121
Changes from 4180A-08/02 to 4180B-04/03 .................................................... 121
Table of Contents .................................................................................. i
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4180B-8051-04/03
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